Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)SOIC 8 1 kBit 128 x 8

 1994-2012 Microchip Technology Inc. DS21095K-page 1

24LC21

Features:

• Single supply with operation down to 2.5V

• Completely implements DDC1

™

/DDC2

™

interface

for monitor identification

• Low-power CMOS technology:

- 1 mA active current typical

-10 A standby current typical at 5.5V

• 2-wire serial interface bus, I

™

compatible

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Factory programming (QTP) available

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges

Description:

The Microchip Technology Inc. 24LC21 is a 128 x 8 bit

Electrically Erasable PROM. This device is designed

for use in applications requiring storage and serial

transmission of configuration and control information.

Two modes of operation have been implemented:

Transmit-only mode and Bidirectional mode. Upon

power-up, the device will be in the Transmit-only mode,

sending a serial bit stream of the entire memory array

contents, clocked by the V

CLK pin. A valid high-to-low

transition on the SCL pin will cause the device to enter

the Bidirectional mode, with byte selectable read/write

capability of the memory array. The 24LC21 is available

in a standard 8-pin PDIP and SOIC package, in both

commercial and industrial temperature ranges.

Package Types

Block Diagram

Commercial (C): 0°C to +70°C

Industrial (I): -40°C to +85°C

24LC21

VCC

VCLK

SCL

SDA

24LC21

VCLK

SCL

SDA

PDIP

SOIC

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp

/W Control

Memory

Control

Logic

I/O

Control

Logic

VCLK

SDA SCL

VCC

VSS

1K 2.5V Dual Mode I

™

Serial EEPROM

Not recommended for new designs –

Please use 24LCS21A.

21095K.book Page 1 Wednesday, December 5, 2012 2:28 PM

Summary of content (24 pages)

PAGE 1
21095K.book Page 1 Wednesday, December 5, 2012 2:28 PM Not recommended for new designs – Please use 24LCS21A. 24LC21 1K 2.5V Dual Mode I2C™ Serial EEPROM Features: PDIP 1 8 VCC NC 2 7 VCLK NC 3 6 SCL VSS 4 5 SDA NC 1 8 VCC NC 2 7 VCLK NC 3 5 SCL VSS 4 5 SDA SOIC 24LC21 Description: The Microchip Technology Inc. 24LC21 is a 128 x 8 bit Electrically Erasable PROM.
PAGE 2
1095K.book Page 2 Wednesday, December 5, 2012 2:28 PM 24LC21 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V Storage temperature ...........................
PAGE 3
21095K.book Page 3 Wednesday, December 5, 2012 2:28 PM 24LC21 TABLE 1-2: AC CHARACTERISTICS Standard Mode Parameter Symbol Vcc= 4.5 - 5.
PAGE 4
21095K.book Page 4 Wednesday, December 5, 2012 2:28 PM 24LC21 2.0 FUNCTIONAL DESCRIPTION The 24LC21 operates in two modes, the Transmit-only mode and the Bidirectional mode. There is a separate two-wire protocol to support each mode, each having a separate clock input and sharing a common data line (SDA). The device enters the Transmit-only mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin.
PAGE 5
21095K.book Page 5 Wednesday, December 5, 2012 2:28 PM 24LC21 3.0 BIDIRECTIONAL MODE 3.1 The 24LC21 can be switched into the Bidirectional mode (see Figure 3-1) by applying a valid high-to-low transition on the Bidirectional mode clock (SCL). When the device has been switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire bidirectional data transmission protocol.
PAGE 6
21095K.book Page 6 Wednesday, December 5, 2012 2:28 PM 24LC21 3.1.4 DATA VALID (D) 3.1.5 The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit.
PAGE 7
21095K.book Page 7 Wednesday, December 5, 2012 2:28 PM 24LC21 3.1.6 SLAVE ADDRESS After generating a Start condition, the bus master transmits the slave address consisting of a 7-bit device code ‘1010’ for the 24LC21, followed by three “don’t care” bits. The eighth bit of slave address determines if the master device wants to read or write to the 24LC21 (Figure 3-5). The 24LC21 monitors the bus for its corresponding slave address all the time.
PAGE 8
21095K.book Page 8 Wednesday, December 5, 2012 2:28 PM 24LC21 It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written.
PAGE 9
21095K.book Page 9 Wednesday, December 5, 2012 2:28 PM 24LC21 FIGURE 4-3: PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S Word Address Control Byte BUS ACTIVITY Data (n + 1) Data (n) S T O P Data (n + 15) P A C K A C K A C K A C K A C K VCLK  1994-2012 Microchip Technology Inc.
PAGE 10
21095K.book Page 10 Wednesday, December 5, 2012 2:28 PM 24LC21 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately.
PAGE 11
21095K.book Page 11 Wednesday, December 5, 2012 2:28 PM 24LC21 7.0 READ OPERATION 7.3 Sequential Read Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read.
PAGE 12
21095K.book Page 12 Wednesday, December 5, 2012 2:28 PM 24LC21 FIGURE 7-2: RANDOM READ S T BUS ACTIVITY A MASTER R T Control Byte S T A R T Word Address S SDA LINE Control Byte S T O P Data (n) P S A C K BUS ACTIVITY A C K A C K N O A C K FIGURE 7-3: BUS ACTIVITY MASTER SEQUENTIAL READ Control Byte Data (n) Data (n + 1) Data (n + 2) S T O P Data (n + X) P SDA LINE BUS ACTIVITY A C K A C K A C K A C K N O A C K DS21095K-page 12  1994-2012 Microchip Technology Inc.
PAGE 13
21095K.book Page 13 Wednesday, December 5, 2012 2:28 PM 24LC21 8.0 PIN DESCRIPTIONS TABLE 8-1: 8.1 PIN FUNCTION TABLE Name Function VSS SDA SCL VCLK VCC NC Ground Serial Address/Data I/O Serial Clock (Bidirectional mode) Serial Clock (Transmit-only mode) +2.5V to 5.5V Power Supply No Connection SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the Bidirectional mode.
PAGE 14
21095K.book Page 14 Wednesday, December 5, 2012 2:28 PM 24LC21 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP Example XXXXXXXX XXXXXNNN YYWW 24LC21 017 0410 8-Lead SOIC (.150”) XXXXXXXX XXXXYYWW NNN Legend: XX...
PAGE 15
21095K.book Page 15 Wednesday, December 5, 2012 2:28 PM 24LC21 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PAGE 16
21095K.book Page 16 Wednesday, December 5, 2012 2:28 PM 24LC21 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PAGE 17
21095K.book Page 17 Wednesday, December 5, 2012 2:28 PM 24LC21 APPENDIX A: REVISION HISTORY Revision J Added note to page 1 header (Not recommended for new designs). Added Section 9.0: Package Marking Information. Added On-line Support page. Updated document format. Revision K Added a note to each package outline drawing.  1994-2012 Microchip Technology Inc.
PAGE 18
21095K.book Page 18 Wednesday, December 5, 2012 2:28 PM 24LC21 NOTES: DS21095K-page 18  1994-2012 Microchip Technology Inc.
PAGE 19
21095K.book Page 19 Wednesday, December 5, 2012 2:28 PM 24LC21 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 20
21095K.book Page 20 Wednesday, December 5, 2012 2:28 PM 24LC21 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
PAGE 21
095K.book Page 21 Wednesday, December 5, 2012 2:28 PM 24LC21 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 22
21095K.book Page 22 Wednesday, December 5, 2012 2:28 PM 24LC21 NOTES: DS21095K-page 22  1994-2012 Microchip Technology Inc.
PAGE 23
21095K.book Page 23 Wednesday, December 5, 2012 2:28 PM Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 24
21095K.book Page 24 Wednesday, December 5, 2012 2:28 PM Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.