Data Sheet

24AA128/24LC128/24FC128
DS20001191U-page 8 2010-2021 Microchip Technology Inc. and its subsidiaries
3.0 FUNCTIONAL DESCRIPTION
The 24XX128 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a host device which generates the Serial
Clock (SCL), controls the bus access and generates
the Start and Stop conditions while the 24XX128 works
as a client. Both host and client can operate as a
transmitter or receiver, but the host device determines
which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the host device and is,
theoretically, unlimited (although only the last 64 will be
stored when doing a write operation). When an
overwrite does occur, it will replace data in a
First-In First-Out (FIFO) principle.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The host device must generate an extra
clock pulse, which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Moreover, setup
and hold times must be taken into account. During
reads, a host must signal an end of data to the client by
not generating an Acknowledge bit on the last byte that
has been clocked out of the client. In this case, the
client (24XX128) will leave the data line high to enable
the host to generate the Stop condition.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX128 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A) (B) (D) (D) (C) (A)