Data Sheet

2010-2021 Microchip Technology Inc. and its subsidiaries DS20001191U-page 5
24AA128/24LC128/24FC128
11 TSU:WP WP Setup Time
4000 ns1.7V V
CC 2.5V
600 ns2.5V VCC 5.5V
600 ns1.7V VCC 5.5V (24FC128)
12 THD:WP WP Hold Time
4700 ns1.7V V
CC 2.5V
1300 ns2.5V VCC 5.5V
1300 ns1.7V VCC 5.5V (24FC128)
13 TAA Output Valid From Clock
3500 ns 1.7V V
CC 2.5V (Note 2)
900 ns 2.5V VCC 5.5V (Note 2)
900 ns
1.7V VCC 2.5V (24FC128)
(Note 2)
400 ns
2.5V VCC 5.5V (24FC128)
(Note 2)
14 TBUF
Bus Free Time: The Time The
Bus Must Be Free Before a
New Transmission Can Start
4700 ns1.7V V
CC 2.5V
1300 ns2.5V VCC 5.5V
1300 ns1.7V VCC 2.5V (24FC128)
500 ns2.5V VCC 5.5V (24FC128)
15 TOF
Output Fall Time from VIH
Minimum to VIL Maximum
CB 100 pF
10 +
0.1CB
250 ns All except, 24FC128 (Note 1)
250 ns 24FC128 (Note 1)
16 TSP
Input Filter Spike Suppression
(SDA and SCL pins)
50ns
All except, 24FC128
(Notes 1 and Note 3)
17 T
WC
Write Cycle Time
(byte or page)
5ms
18 Endurance 1,000,000 cycles +25°C, 5.5V, Page Mode (Note 4)
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Extended (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No.
Symbol Characteristic Minimum Maximum Units Conditions
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization.