Datasheet
Table Of Contents
- 24AA1025/24LC1025/24FC1025
- Device Selection Table:
- Features:
- Description:
- Package Type
- Block Diagram
- 1.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- TABLE 1-1: DC Characteristics
- TABLE 1-2: AC Characteristics
- Note 1: Not 100% tested. Cb = total capacitance of one bus line in pF.
- 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
- 3: The combined Tsp and Vhys specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.
- 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
- FIGURE 1-1: Bus Timing Data
- Absolute Maximum Ratings(†)
- 2.0 Pin Descriptions
- 3.0 Functional Description
- 4.0 Bus Characteristics
- 5.0 Device Addressing
- 6.0 Write Operations
- 7.0 Acknowledge Polling
- 8.0 Read Operation
- 9.0 Packaging Information
- Appendix A: Revision History
- Product ID System
- Trademarks
- Worldwide Sales
24AA1025/24LC1025/24FC1025
DS20001941L-page 6 2005-2013 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The 24XX1025 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1025 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.