Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)1024 kBit 128 K x 8

 2005-2012 Microchip Technology Inc. DS21941K-page 1

24AA1025/24LC1025/24FC1025

Device Selection Table:

Features:

• Low-Power CMOS Technology:

- Read current 450 A, maximum

- Standby current 5 A, maximum

• 2-Wire Serial Interface, I

C™ Compatible

• Cascadable up to Four Devices

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kHz and 400 kHz Clock Compatibility

• 1 MHz Clock for FC Versions

• Page Write Time 3 ms, typical

• Self-Timed Erase/Write Cycle

• 128-Byte Page Write Buffer

• Hardware Write-Protect

• ESD Protection >400V

• More than 1 Million Erase/Write Cycles

• Data Retention >200 Years

• Factory Programming Available

• Packages include 8-lead PDIP, SOIJ and SOIC

• Pb-Free and RoHS Compliant

• Temperature Ranges:

- Industrial (I): -40C to +85C

- Automotive (E): -40C to +125C

Description:

The Microchip Technology Inc. 24AA1025/24LC1025/

24FC1025 (24XX1025*) is a 128K x 8 (1024K bit)

Serial Electrically Erasable PROM, capable of

operation across a broad voltage range (1.7V to 5.5V).

It has been developed for advanced, low-power

applications such as personal communications or data

acquisition. This device has both byte write and page

write capability of up to 128 bytes of data.

This device is capable of both random and sequential

reads. Reads may be sequential within address

boundaries 0000h to FFFFh and 10000h to 1FFFFh.

Functional address lines allow up to four devices on the

same data bus. This allows for up to 4 Mbits total

system EEPROM memory. This device is available in

the standard 8-pin PDIP, SOIC and SOIJ packages.

Package Type

Block Diagram

*24XX1025 is used in this document as a generic part number

for the 24AA1025/24LC1025/24FC1025 devices.

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

24AA1025 1.7-5.5V 400 kHz

†

24LC1025 2.5-5.5V 400 kHz* I, E

24FC1025 1.8-5.5V 1 MHz

‡

†

100 kHz for VCC < 2.5V

*100 kHz for V

CC < 4.5V, E-temp

‡

400 kHz for VCC < 2.5V

A2*

VCC

SCL

SDA

PDIP

SOIJ/SOIC

A2*

SCL

SDA

*A2 must be tied to V

CC.

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense AMP

R/W

Control

Memory

Control

Logic

I/O

Control

Logic

I/O

A0 A1

SDA

SCL

1024K I

™

Serial EEPROM

Summary of content (28 pages)

PAGE 1
24AA1025/24LC1025/24FC1025 1024K I2C™ Serial EEPROM Device Selection Table: Part Number VCC Range Max. Clock Frequency 24AA1025 1.7-5.5V 400 kHz† I 24LC1025 2.5-5.5V 400 kHz* I, E 24FC1025 1.8-5.5V 1 MHz‡ I Temp. Ranges † 100 kHz for VCC < 2.5V *100 kHz for VCC < 4.5V, E-temp ‡400 kHz for VCC < 2.5V This device is capable of both random and sequential reads. Reads may be sequential within address boundaries 0000h to FFFFh and 10000h to 1FFFFh.
PAGE 2
4AA1025/24LC1025/24FC1025 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS .......................................................................................................... -0.6V to VCC+1.0V Storage temperature ...............................................................
PAGE 3
24AA1025/24LC1025/24FC1025 TABLE 1-2: AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C AC CHARACTERISTICS Param. No. Sym. Characteristic Min. Max. Units Conditions 1 FCLK Clock frequency — — — — — 100 100 400 400 1000 kHz 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.
PAGE 4
24AA1025/24LC1025/24FC1025 AC CHARACTERISTICS (Continued) Param. No. Sym. Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C Characteristic Min. Max. Units Conditions 11 TSU:WP WP setup time 4000 4000 600 600 600 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 12 THD:WP WP hold time 4700 4700 1300 1300 1300 — — — — — ns 1.
PAGE 5
24AA1025/24LC1025/24FC1025 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: 2.1 PIN FUNCTION TABLE Name PDIP SOIJ SOIC Function A0 1 1 1 User Configurable Chip Select A1 2 2 2 User Configurable Chip Select A2 3 3 3 Non-Configurable Chip Select. This pin must be hard-wired to logical 1 state (VCC). Operation will be undefined with this pin left floating or held to logical 0 (VSS).
PAGE 6
24AA1025/24LC1025/24FC1025 3.0 FUNCTIONAL DESCRIPTION The 24XX1025 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions while the 24XX1025 works as a slave.
PAGE 7
24AA1025/24LC1025/24FC1025 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition.
PAGE 8
24AA1025/24LC1025/24FC1025 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24XX1025, this is set as ‘1010’ binary for read and write operations. The next bit of the control byte is the block select bit (B0). This bit acts as the A16 address bit for accessing the entire array. The next two bits of the control byte are the Chip Select bits (A1, A0).
PAGE 9
24AA1025/24LC1025/24FC1025 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the master, the control code (four bits), the block select (one bit), the Chip Select (two bits), and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle.
PAGE 10
24AA1025/24LC1025/24FC1025 FIGURE 6-1: BYTE WRITE S T A R T BUS ACTIVITY MASTER Control Byte Address High Byte Address Low Byte S T O P Data AA S1 01 0B 010 0 SDA LINE P A C K BUS ACTIVITY A C K A C K A C K X = “don’t care” bit FIGURE 6-2: PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE BAA S101 00100 BUS ACTIVITY Control Byte Address High Byte Address Low Byte Data Byte 0 S T O P Data Byte 127 P A C K A C K A C K A C K A C K X = “don’t care” bit DS21941K-page 10  2005
PAGE 11
24AA1025/24LC1025/24FC1025 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete. (This feature can be used to maximize bus throughput.) Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0).
PAGE 12
24AA1025/24LC1025/24FC1025 8.0 READ OPERATION 8.2 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX1025 contains an address counter that maintains the address of the last word accessed, internally incremented by one.
PAGE 13
24AA1025/24LC1025/24FC1025 FIGURE 8-2: BUS ACTIVITY MASTER SDA LINE RANDOM READ S T A R T Control Byte S 1 0 1 0 BUS ACTIVITY MASTER S T A R T Address Low Byte B A A 0 0 1 0 Control Byte S T O P Data Byte S 1 0 1 0 B A A1 0 1 0 A C K A C K BUS ACTIVITY FIGURE 8-3: Address High Byte A C K P N O A C K A C K SEQUENTIAL READ Control Byte Data n Data n + 1 S T O P Data n + X Data n + 2 P SDA LINE BUS ACTIVITY A C K  2005-2012 Microchip Technology Inc.
PAGE 14
24AA1025/24LC1025/24FC1025 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX TXXXXNNN YYWW 24LC1025 I/P e3 13F 0928 8-Lead SOIC (3.90 mm) 8-Lead SOIJ (5.28 mm) Legend: XX...
PAGE 15
24AA1025/24LC1025/24FC1025 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; < & & 7: 1 , = = - 1 ! & & = = .
PAGE 16
24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21941K-page 16  2005-2012 Microchip Technology Inc.
PAGE 17
24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2012 Microchip Technology Inc.
PAGE 18
24AA1025/24LC1025/24FC1025 ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS21941K-page 18  2005-2012 Microchip Technology Inc.
PAGE 19
24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2012 Microchip Technology Inc.
PAGE 20
24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21941K-page 20  2005-2012 Microchip Technology Inc.
PAGE 21
24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2012 Microchip Technology Inc.
PAGE 22
24AA1025/24LC1025/24FC1025 APPENDIX A: REVISION HISTORY Revision A (02/2005) Original release. Revision B (09/2005) Section 1.0 Electrical Characteristics: revised Ambient Temperature; Revised Table 1-1; Revised Section 2.1 and Section 2.5. Revision C (04/2006) Revised Features, Maximum Read Current and Table 1-1, D9; Revised Table 2-1, VCC; Revised Section 6.3. Revision D (01/2007) Revised Device Selection Table; Features Section; Changed 1.8V to 1.
PAGE 23
24AA1025/24LC1025/24FC1025 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 24
AA1025/24LC1025/24FC1025 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 25
24AA1025/24LC1025/24FC1025 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Temperature Range Package Examples: a) b) Device: 24AA1025 = 24AA1025T = 24LC1025 = 24LC1025T = 24FC1025 = 24FC1025T = 1024K Bit 1.7V I2C CMOS Serial EEPROM 1024K Bit 1.7V I2C CMOS Serial EEPROM (Tape and Reel) 1024K Bit 2.5V I2C CMOS Serial EEPROM 1024K Bit 2.
PAGE 26
24AA1025/24LC1025/24FC1025 NOTES: DS21941K-page 26  2005-2012 Microchip Technology Inc.
PAGE 27
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 28
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