Datasheet
Table Of Contents
- 24AA1025/24LC1025/24FC1025
- Device Selection Table:
- Features:
- Description:
- Package Type
- Block Diagram
- 1.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- TABLE 1-1: DC Characteristics
- TABLE 1-2: AC Characteristics
- Note 1: Not 100% tested. Cb = total capacitance of one bus line in pF.
- 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
- 3: The combined Tsp and Vhys specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.
- 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
- FIGURE 1-1: Bus Timing Data
- Absolute Maximum Ratings(†)
- 2.0 Pin Descriptions
- 3.0 Functional Description
- 4.0 Bus Characteristics
- 5.0 Device Addressing
- 6.0 Write Operations
- 7.0 Acknowledge Polling
- 8.0 Read Operation
- 9.0 Packaging Information
- Appendix A: Revision History
- Product ID System
- Trademarks
- Worldwide Sales
2005-2013 Microchip Technology Inc. DS20001941L-page 5
24AA1025/24LC1025/24FC1025
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Tab le 2- 1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1 Chip Address Inputs
The A0 and A1 inputs are used by the 24XX1025 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2 A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to V
CC in order for this device to operate.
If left floating or tied to V
SS, device operation will be
undefined.
2.3 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
CC (typical 10 k for 100kHz, 2kfor
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.4 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.5 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to V
SS, write operations are enabled. If tied to VCC,
write operations are inhibited, but read operations are
not affected.
Name PDIP SOIJ SOIC Function
A0 1 1 1 User Configurable Chip Select
A1 2 2 2 User Configurable Chip Select
A2 3 3 3 Non-Configurable Chip Select.
This pin must be hard-wired to logical 1 state (V
CC). Operation will
be undefined with this pin left floating or held to logical 0 (V
SS).
V
SS 4 4 4 Ground
SDA 5 5 5 Serial Data
SCL 6 6 6 Serial Clock
WP 7 7 7 Write-Protect Input
V
CC 8 8 8 +1.7 to 5.5V (24AA1025)
+2.5 to 5.5V (24LC1025)
+1.8 to 5.5V (24FC1025)