Datasheet
Table Of Contents
- 24AA1025/24LC1025/24FC1025
- Device Selection Table:
- Features:
- Description:
- Package Type
- Block Diagram
- 1.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- TABLE 1-1: DC Characteristics
- TABLE 1-2: AC Characteristics
- Note 1: Not 100% tested. Cb = total capacitance of one bus line in pF.
- 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
- 3: The combined Tsp and Vhys specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.
- 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
- FIGURE 1-1: Bus Timing Data
- Absolute Maximum Ratings(†)
- 2.0 Pin Descriptions
- 3.0 Functional Description
- 4.0 Bus Characteristics
- 5.0 Device Addressing
- 6.0 Write Operations
- 7.0 Acknowledge Polling
- 8.0 Read Operation
- 9.0 Packaging Information
- Appendix A: Revision History
- Product ID System
- Trademarks
- Worldwide Sales
2005-2013 Microchip Technology Inc. DS20001941L-page 11
24AA1025/24LC1025/24FC1025
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete. (This feature can be used to maximize bus
throughput.) Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W
= 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be resent. If the cycle is complete, then the device
will return the ACK and the master can then proceed
with the next Read or Write command. See Figure 7-1
for flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Note: Care must be taken when polling the
24XX1025. The control byte that was
used to initiate the write needs to match
the control byte used for polling.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes