Information

www.microchip.com/memory
10
NOR Flash
What is SuperFlash Technology?
Microchip’s SuperFlash technology is an innovative, highly
reliable and versatile type of NOR Flash memory. SuperFlash
technology memory is much more exible and reliable than
competing non-volatile memories. This technology utilizes a
split-gate cell architecture which uses a robust thick-oxide
process that requires fewer mask steps resulting in a lower-
cost nonvolatile memory solution with extremely fast erase
time, excellent data retention and higher reliability.
SuperFlash Technology Advantages
• Fast, xed program and erase times
•
~ 40 ms for SuperFlash technology vs. more than a
minute for conventional 64 Mbits
•
Results in improved manufacturing eciency and lower costs
• No pre-programming or verication required prior to erase
•
Results in signicantly lower power consumption
• Superior reliability
•
100 K cycles and 100 years data retention
• Inherent small-sector size
•
4 KB erase sector vs. 64 KB
•
Results in faster re-write operations and contributes to
lowering overall power consumption
Serial and Parallel Flash
Serial Flash (25 and 26 Series) are designed for a wide variety
of applications in consumer electronics, computing, networking
and industrial spaces. Small form factor, standard pinouts and
command sets make Serial Flash easy to design in and cost
competitive.
Our Parallel Flash (39 and 38 Series) are ideal for
GPS/navigation and other mobile devices that require Execute-
in-Place (XIP) performance and for demanding industrial and
automotive applications.
8 MB Firmware Flash
Microchip is the sole remaining supplier of 8 Mb Firmware
Flash. This SuperFlash technology memory device is compliant
with the Intel Low Pin Count (LPC) Interface Specication and
is intended to store system BIOS in applications such as PCs,
point-of-sale systems, set-top boxes, network boards and
other embedded CPU applications.
• FWH devices (49LF008A) incorporate Intel’s proprietary
FWH interface protocol used in the Intel 8XX Series Hub
Architecture chipsets.
• LPC Flash devices (49LF080A) comply with the standard
Intel Low Pin Count Interface Specication 1.1.
Memory Cell Structure Comparison
100× Times Faster Erase Times Than
Competitors and Chip Erase Time Remains the
Same Across All Densities
Source
Th
icker tunnel
ox
ide reduces
leakage
improving data
retention and
reliability.
Drain
Poly 2
Split Gate
SuperFlash
®
Technology
Poly 2
Poly 1
Source Drain
Stacked Gate
(Conventional Flash)
Poly 1
0.5 124816 32 64
0.01
0.1
1
10
100
100
Density (MB)
Microchip
Competitor 1 Competitor 2 Competitor 3 Competitor 4