Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)EEPROM (Serial) Case type DIP-8



1996 Microchip Technology Inc. DS21058G-page 1

FEATURES

• Voltage operating range: 4.5V to 5.5V

- Peak write current 3 mA at 5.5V

- Maximum read current 150

A at 5.5V

- Standby current 1

A typical

• Industry standard two-wire bus protocol, I



compatible

• 8 byte page, or byte modes available

• 2 ms typical write cycle time, byte or page

• 64-byte input cache for fast write loads

• Up to eight devices may be connected to the

same bus for up to 512K bits total memory

• Including 400 KHz compatibility

• Programmable block security options

• Programmable endurance options

• Schmitt trigger, ﬁltered inputs for noise suppres-

sion

• Output slope control to eliminate ground bounce

• Self-timed ERASE and WRITE cycles

• Power on/off data protection circuitry

• Endurance:

- 10,000,000 E/W cycles guaranteed for High

Endurance Block

- 100,000 E/W cycles guaranteed for a Stan-

dard Endurance Block

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP/SOIC packages

• Temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24C65 is a “smart” 8K x

8 Serial Electrically Erasable PROM (EEPROM). This

device has been developed for advanced, low power

applications such as personal communications, and

provides the systems designer with ﬂexibility through

the use of many new user-programmable features. The

24C65 offers a relocatable 4K bit block of

ultra-high-endurance memory for data that changes

frequently. The remainder of the array, or 60K bits, is

rated at 1,000,000 ERASE/WRITE (E/W) cycles guar-

anteed. The 24C65 features an input cache for fast

write loads with a capacity of eight pages, or 64 bytes.

This device also features programmable security

- Commercial (C): 0

C to +70

- Industrial (I) -40

C to +85

- Automotive (E): -40

C to +125

options for E/W protection of critical data and/or code of

up to ﬁfteen 4K blocks. Functional address lines allow

the connection of up to eight 24C65's on the same bus

for up to 512K bits contiguous EEPROM memory.

Advanced CMOS technology makes this device ideal

for low-power nonvolatile code and data applications.

The 24C65 is available in the standard 8-pin plastic DIP

and 8-pin surface mount SOIC package.

24C65

64K 5.0V I



Smart Serial



EEPROM

PACKAGE TYPES

BLOCK DIAGRAM

24C65

VCC

SCL

SDA

24C65

SCL

SDA

PDIP

SOIC

HV Generator

EEPROM ARRAY

Page Latches

Cache

YDEC

Vcc

Vss

I/O

Control

Logic

Memory

Control

Logic

SCL

SDA

A0..A2



XDEC

Sense AMP 

R/W Control

I/O

C is a trademark of Philips Corporation.

Smart Serial is a trademark of Microchip Technology Inc.

This document was created with FrameMaker404

Summary of content (17 pages)

PAGE 1
24C65 64K 5.0V I2C Smart Serial EEPROM FEATURES PACKAGE TYPES PDIP A0 1 8 VCC A1 2 7 NC A2 3 6 SCL VSS 4 5 SDA A0 1 8 VCC A1 2 7 NC A2 3 6 SCL VSS 4 9 SDA 24C65 SOIC 24C65 • Voltage operating range: 4.5V to 5.5V - Peak write current 3 mA at 5.5V - Maximum read current 150 µA at 5.
PAGE 2
4C65 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name A0..A2 VSS SDA SCL VCC NC VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied ................ -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins ...............
PAGE 3
24C65 TABLE 1-3: AC CHARACTERISTICS STD.
PAGE 4
24C65 2.0 FUNCTIONAL DESCRIPTION The 24C65 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C65 works as slave.
PAGE 5
24C65 Device Addressing 3.6 A control byte is the first byte received following the start condition from the master device. The control byte consists of a four bit control code, for the 24C65 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three most significant bits of the word address.
PAGE 6
24C65 FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8-2) S T BUS A ACTIVITY: R MASTER T WORD ADDRESS (1) CONTROL BYTE SDA LINE WORD ADDRESS (0) S T O P DATA n+7 DATA n 0 0 0 A C K A C K BUS ACTIVITY: FIGURE 4-3: A C K A C K A C K CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE S T O P DATA n P A C K BUS ACTIVITY N O A C K FIGURE 4-4: S T A R T RANDOM READ WORD ADDRESS (1) CONTROL BYTE FIGURE 4-5: BUS ACTIVITY MASTER WORD ADDRESS (0) CONTROL B
PAGE 7
24C65 5.0 READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 5.1 Current Address Read The 24C65 contains an address counter that maintains the address of the last word accessed, internally incremented by one.
PAGE 8
24C65 define the number of blocks to be write protected. For example, if three blocks are to be protected, the third byte would be 10XX0011. After the third byte is sent to the device, it will acknowledge and a STOP bit is then sent by the master to complete the command. During a normal write sequence, if an attempt is made to write to a protected address, no data will be written and the device will not report an error or abort the command.
PAGE 9
24C65 7.0 PAGE CACHE AND ARRAY MAPPING The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer. The cache allows the loading of up to 64 bytes of data before the write cycle is actually begun, effectively providing a 64-byte burst write at the maximum bus rate. Whenever a write command is initiated, the cache starts loading and will continue to load until a stop bit is received to start the internal write cycle.
PAGE 10
24C65 FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS Control Byte Address Byte 1 Address Byte 0 1 0 1 0 A A A R 2 1 0 W S 0 0 A A A A A 12 11 10 9 8 A A 7 • • • • • • 0 Configuration Byte R X X B B B B 3 2 1 0 S/HE Slave Device Address Select Bits Block Count Security Read S t a r t Acknowledge from Master Acknowledges from Device Data from Device R No ACK S t Data from Device o p A A A A A 1 0 1 0 A A A 0 C 1 X X X X X X X C X X X X X X X X C 1 1 X X X X X X C 1 1 1 1 B B B B C 1 1 1 1 N N N
PAGE 11
24C65 FIGURE 8-2: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY 1 Write command initiated at byte 0 of page 3 in the array; First data byte is loaded into the cache byte 0. 2 64 bytes of data are loaded into cache. cache page 0 cache byte 0 cache byte 1 cache byte 7 • • • cache page 1 cache page 2 bytes 8-15 bytes 16-23 3 Write from cache into array initiated by STOP bit. Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written.
PAGE 12
24C65 NOTES: DS21058G-page 12  1996 Microchip Technology Inc.
PAGE 13
24C65 NOTES:  1996 Microchip Technology Inc.
PAGE 14
24C65 NOTES: DS21058G-page 14  1996 Microchip Technology Inc.
PAGE 15
24C65 24C65 Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24C65 – /P Package: Temperature Range: Device:  1996 Microchip Technology Inc.
PAGE 16
WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc.
PAGE 17
Microchip 64K to 128K: First page of 24C65 datasheet Seite 1 von 1 24C65 Overview #### Note: The Microchip name and logo, PIC, PICMASTER, PRO MATE, PICSTART and KEELOQ are registered trademarks of Microchip Technology Inc. in the USA and other countries. SQTP is a servicemark of Microchip Technology Inc. in the USA and other countries. PICmicro and MPLAB are trademarks of Microchip Technology Inc. in the USA and other countries. Windows is a registered trademark of Microsoft Corporation.