Datasheet

24AA65/24LC65/24C65
DS21073K-page 12 © 2008 Microchip Technology Inc.
FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS
A
1
Control Byte
A
2
A
0
R/W
0101
A
10
Address Byte 1
A
11
A
9
A
8
00S
A
7
A
0
•••
Address Byte 0
Slave
Address
Device
Select
Bits
•••
A
12
B
2
Configuration Byte
B
3
B
1
B
0
XR
X
Block
Count
S/HE
A
1
A
2
A
0
0101
X
XXX
XX1
X
Starting Block
Number
S
t
a
r
t
0
X
XXX
XX
X
X
A
C
K
X
XXX
X11
X
A
C
K
B
2
B
3
B
1
B
0
111
1
N
2
N
3
N
1
N
0
111
1
Number of
Blocks to
Protect
S
t
o
p
A
C
K
No
ACK
Data from Device
Acknowledge
from
Master
Data from Device
Acknowledges from Device
A
1
A
2
A
0
0101
B
1
B
2
B
0
X
XX1
B
3
S
t
a
r
t
0
X
XXX
XX
X
X
N
2
N
3
N
1
N
0
X01
X
A
C
K
S
t
o
p
Acknowledges from Device
A
1
A
2
A
0
A
C
K
0101
X
XXX
XX1
X
High Endurance
Block Number
S
t
a
r
t
0
X
XXX
XX
X
X
A
C
K
X
XXX
X10
X
A
C
K
B
2
B
3
B
1
B
0
111
1
S
t
o
p
A
C
K
No
ACK
Data from Device
Acknowledges from Device
A
1
A
2
A
0
A
C
K
0101
B
1
B
2
B
0
X
XX1
B
3
S
t
a
r
t
0
X
XXX
XX
X
X
A
C
K
0
000
X00
X
A
C
K
S
t
o
p
A
C
K
Acknowledges from Device
Starting Block
Number
Number of
Blocks to
Protect
R
S/HE
R
S/HE
R
S/HE
R
S/HE
Security Read
Security Write
High Endurance Block Read
High Endurance Block Write
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
High Endurance
Block Number