Datasheet
© 2007 Microchip Technology Inc. DS21178G-page 3
24AA00/24LC00/24C00
TABLE 1-2: AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Industrial (I): T
A = -40°C to +85°C, VCC = 1.8V to 5.5V
Automotive (E): T
A = -40°C to +125°C, VCC = 4.5V to 5.5V
Parameter Symbol Min Max Units Conditions
Clock frequency F
CLK —
—
—
100
100
400
kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Clock high time THIGH 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Clock low time TLOW 4700
4700
1300
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL rise time
(Note 1)
TR —
—
—
1000
1000
300
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL fall time TF —300ns(Note 1)
Start condition hold time THD:STA 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Start condition setup time TSU:STA 4700
4700
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Data input hold time THD:DAT 0—ns(Note 2)
Data input setup time T
SU:DAT 250
250
100
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Stop condition setup time T
SU:STO 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output valid from clock
(Note 2)
T
AA —
—
—
3500
3500
900
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
T
BUF 4700
4700
1300
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output fall time from V
IH
minimum to VIL maximum
T
OF 20+0.1
CB
250 ns (Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP —50ns(Notes 1, 3)
Write cycle time T
WC —4ms
Endurance 1M — cycles (Note 4)
Note 1: Not 100% tested. C
B = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.