Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)SOT 23-3 2 kBit 256 x 8

 2008-2013 Microchip Technology Inc. DS20002122B-page 1

11AA02E48/11AA02E64

DEVICE SELECTION TABLE

Features:

• Pre-programmed Globally Unique, 48-bit or 64-bit

Node Address

• Compatible with EUI-48™ and EUI-64™

• Single I/O, UNI/O

Serial Interface Bus

• Low-Power CMOS Technology

- 1 mA active current, typical

- 1 µA standby current (max.)

• 256 x 8 Bit Organization

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kbps Max. Bit Rate – Equivalent to 100 kHz

Clock Frequency

• Self-Timed Write Cycle (including Auto-Erase)

• Page-Write Buffer for up to 16 Bytes

• STATUS Register for Added Control:

- Write enable latch bit

- Write-In-Progress bit

• Block Write Protection

- Protect none, 1/4, 1/2 or all of array

• Built-in Write Protection

- Power-on/off data protection circuitry

- Write enable latch

• High Reliability

- Endurance: 1,000,000 erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4,000V

• 3-lead SOT-23 and 8-lead SOIC Packages

• Pb-Free and RoHS Compliant

• Available Temperature Ranges:

Description:

The Microchip Technology Inc. 11AA02E48/

11AA02E64 (11AA02EXX*) device is a 2 Kbit Serial

Electrically Erasable PROM. The device is organized in

blocks of x8-bit memory and support the patented**

single I/O UNI/O

serial bus. By using Manchester

encoding techniques, the clock and data are combined

into a single, serial bit stream (SCIO), where the clock

signal is extracted by the receiver to correctly decode

the timing and value of each bit.

Low-voltage design permits operation down to 1.8V,

with standby and active currents of only 1 uA and 1 mA,

respectively.

The 11AA02EXX is available in standard 8-lead

SOIC and 3-lead SOT-23 packages.

Package Types (not to scale)

Pin Function Table

Part Number

Density

(bits)

VCC Range

Page Size

(Bytes)

Temp.

Ranges

Packages Node Address

11AA02E48 2K 1.8-5.5V 16 I

SN, TT EUI-48™

11AA02E64 2K 1.8-5.5V 16 I

SN, TT EUI-64™

- Industrial (I): -40°C to +85°C

Name Function

SCIO Serial Clock, Data Input/Output

SS Ground

VCC Supply Voltage

VSS

VCC

SCIO

SOIC

(SN)

SOT23

SCIO

VSS

(TT)

2K UNI/O

Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity

* 11AA02EXX is used in this document as a generic part number for the 11AA02E48 and 11AA02E64 devices.

** Microchip’s UNI/O

Bus products are covered by the following patents issued in the U.S.A.: 7,376,020 and 7,788,430.

Summary of content (32 pages)

PAGE 1
1AA02E48/11AA02E64 2K UNI/O® Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity DEVICE SELECTION TABLE Part Number Density (bits) VCC Range Page Size (Bytes) Temp. Ranges Packages Node Address 11AA02E48 2K 1.8-5.5V 16 I SN, TT EUI-48™ 11AA02E64 2K 1.8-5.
PAGE 2
11AA02E48/11AA02E64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V SCIO w.r.t. VSS .................................................................................................................................... -0.6V to VCC+1.0V Storage temperature .............................................................
PAGE 3
11AA02E48/11AA02E64 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = 2.5V to 5.5V VCC = 1.8V to 2.5V AC CHARACTERISTICS Param. No. Sym. 1 FBUS 2 TE 3 TIJIT Characteristic Min. Max. Units Serial Bus Frequency 10 100 kHz Bit Period 10 100 µs — Input Edge Jitter Tolerance — ±0.06 UI (Note 3) — ±0.
PAGE 4
11AA02E48/11AA02E64 FIGURE 1-1: 10 BUS TIMING – START HEADER 11 2 SCIO Data ‘0’ FIGURE 1-2: Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit BUS TIMING – DATA 2 7 8 Data ‘1’ Data ‘0’ 12 SCIO Data ‘0’ FIGURE 1-3: Data ‘1’ Data ‘1’ BUS TIMING – STANDBY PULSE 9 SCIO Standby Mode FIGURE 1-4: BUS TIMING – JITTER 2 3 Ideal Edge from Master DS20002122B-page 4 2 3 Ideal Edge from Master 6 6 Ideal Edge from Slave 6 6 Ideal Edge from Slave  2008-2013 Microch
PAGE 5
11AA02E48/11AA02E64 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 11AA02EXX family of serial EEPROMs support the UNI/O® protocol. They can be interfaced with microcontrollers, including Microchip’s PIC® microcontrollers, ASICs, or any other device with an available discrete I/O line that can be configured properly to match the UNI/O protocol. The 11AA02EXX devices contain an 8-bit instruction register. The devices are accessed via the SCIO pin.
PAGE 6
11AA02E48/11AA02E64 3.0 BUS CHARACTERISTICS 3.1 Standby Pulse If a command is terminated in any manner other than a NoMAK/SAK combination, then the master must perform a standby pulse before beginning a new command, regardless of which device is to be selected. When the master has control of SCIO, a standby pulse can be generated by holding SCIO high for TSTBY. At this time, the 11AA02EXX will reset and return to Standby mode.
PAGE 7
11AA02E48/11AA02E64 3.3 Acknowledge FIGURE 3-4: MAK (‘1’) SAK (‘1’) NoMAK (‘0’) NoSAK(1) An Acknowledge routine occurs after each byte is transmitted, including the start header. This routine consists of two bits. The first bit is transmitted by the master, and the second bit is transmitted by the slave. Note: A MAK must always be transmitted following the start header.
PAGE 8
11AA02E48/11AA02E64 3.6 Device Standby The 11AA02EXX features a low-power Standby mode during which the device is waiting to begin a new command. A high-to-low transition on SCIO will exit lowpower mode and prepare the device for receiving the start header. Standby mode will be entered upon the following conditions: • A NoMAK followed by a SAK (i.e., valid termination of a command) • Reception of a standby pulse Note: 3.
PAGE 9
11AA02E48/11AA02E64 4.0 DEVICE COMMANDS After the device address byte, a command byte must be sent by the master to indicate the type of operation to be performed. The code for each instruction is listed in Table 4-1.
PAGE 10
11AA02E48/11AA02E64 Current Address Read (CRRD) Instruction TABLE 4-2: The internal address counter featured on the 11AA02EXX maintains the address of the last memory array location accessed. The CRRD instruction allows the master to read data back beginning from this current location. Consequently, no word address is provided upon issuing this command.
PAGE 11
AA02E48/11AA02E64 Write Instruction Prior to any attempt to write data to the 11AA02EXX, the write enable latch must be set by issuing the WREN instruction (see Section 4.4 “Write Enable (WREN) and Write Disable (WRDI) Instructions”). Once the write enable latch is set, the user may proceed with issuing a WRITE instruction (including the header and device address bytes) followed by the MSB and LSB of the Word Address.
PAGE 12
11AA02E48/11AA02E64 Write Enable (WREN) and Write Disable (WRDI) Instructions The 11AA02EXX contains a write enable latch. See Table 6-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI instruction will reset the latch. The WREN and WRDI instructions must be terminated with a NoMAK following the command byte.
PAGE 13
11AA02E48/11AA02E64 Read Status Register (RDSR) Instruction The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user through the WRSR instruction. These bits are nonvolatile. The RDSR instruction provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle.
PAGE 14
11AA02E48/11AA02E64 Write Status Register (WRSR) Instruction TABLE 4-3: The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as illustrated in Table 4-3.
PAGE 15
11AA02E48/11AA02E64 Erase All (ERAL) Instruction The ERAL instruction allows the user to write ‘0x00’ to the entire memory array with one command. Note that the write enable latch (WEL) must first be set by issuing the WREN instruction. The ERAL instruction is ignored if either of the Block Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or all of the array is protected.
PAGE 16
11AA02E48/11AA02E64 5.0 DATA PROTECTION The following protection has been implemented to prevent inadvertent writes to the array: • The Write Enable Latch (WEL) is reset on powerup • A Write Enable (WREN) instruction must be issued to set the write enable latch • After a write, ERAL, SETAL, or WRSR command, the write enable latch is reset • Commands to access the array or write to the status register are ignored during an internal write cycle and programming is not affected 6.
PAGE 17
11AA02E48/11AA02E64 7.0 PRE-PROGRAMMED EUI-48™ OR EUI-64™ NODE ADDRESS The 11AA02EXX is programmed at the factory with a globally unique node address stored in the upper 1/4 of the array and write-protected through the STATUS register. The remaining 1,536 bits are available for application use. FIGURE 7-1: MEMORY ORGANIZATION 00h Standard EEPROM Write-Protected Node Address Block 7.
PAGE 18
11AA02E48/11AA02E64 7.3 EUI-64™ Node Address (11AA02E64) The remaining five bytes are the Extension Identifier, and are generated by Microchip to ensure a globallyunique, 64-bit value. The 8-byte EUI-64™ node address value of the 11AA02E64 is stored in array locations 0xF8 through 0xFF, as shown in Figure 7-3. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority.
PAGE 19
11AA02E48/11AA02E64 8.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 8-1. TABLE 8-1: Name PIN FUNCTION TABLE 3-pin SOT-23 8-pin SOIC SCIO 1 5 Serial Clock, Data Input/Output VCC 2 8 Supply Voltage Ground VSS 3 4 NC — 1,2,3,6,7 8.1 Description No Internal Connection Serial Clock, Data Input/Output (SCIO) SCIO is a bidirectional pin used to transfer commands and addresses into, as well as data into and out of, the device.
PAGE 20
11AA02E48/11AA02E64 9.0 PACKAGING INFORMATION 9.1 Package Marking Information Example: 8-Lead SOIC 11A2E48I SN e3 1328 1L7 XXXXXXXT XXXXYYWW NNN 3-Lead SOT-23 (11AA02E48) Example: XXNN E217 3-Lead SOT-23 (11AA02E64) Example: XXXNNN AAA1L7 1st Line Marking Code Part Number SOT-23 SOIC I Temp. I Temp. 11AA02E48 E2NN 11A2E48T 11AA02E64 AAANNN 11A2E64T Legend: XX...
PAGE 21
11AA02E48/11AA02E64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc.
PAGE 22
11AA02E48/11AA02E64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002122B-page 22  2008-2013 Microchip Technology Inc.
PAGE 23
11AA02E48/11AA02E64 & ! " #$% ! " # $ % & "' " " ( $ ) % *++&&& ! !+ $  2008-2013 Microchip Technology Inc.
PAGE 24
11AA02E48/11AA02E64 & ' '' " ' ( % ! " # $ % & "' " " ( $ ) % *++&&& ! !+ $ b N E E1 2 1 e e1 D c A φ A2 A1 L > " ! " ? ! " @#!G ) ( " ?? 3 3 @ @A E @ H ? % ( 7 ; < A# " % ? % ( 1 A= J K 7 1 1 1 K 1 % % ( $ $ "" % )) 1 ; < 1 1 A= L % 3 1 K
PAGE 25
11AA02E48/11AA02E64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc.
PAGE 26
11AA02E48/11AA02E64 APPENDIX A: REVISION HISTORY Revision A (12/2008) Original release of this document. Revision B (04/2013) Revised AC Char. Max. Parameters 3 and 4; Added 11AA02E64 part. DS20002122B-page 26  2008-2013 Microchip Technology Inc.
PAGE 27
11AA02E48/11AA02E64 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 28
11AA02E48/11AA02E64 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 29
11AA02E48/11AA02E64 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X X /XX Tape & Reel Temperature Package Range Examples: a) b) Device: 11AA02E48 = 11AA02E64 = 2 Kbit, 1.8V UNI/O Serial EEPROM with EUI-48™ Node Identity 2 Kbit, 1.
PAGE 30
11AA02E48/11AA02E64 NOTES: DS20002122B-page 30  2008-2013 Microchip Technology Inc.
PAGE 31
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 32
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