Datasheet

 2011 Microchip Technology Inc. DS22067J-page 17

11XX

5.0 DATA PROTECTION

The following protection has been implemented to

prevent inadvertent writes to the array:

• The Write Enable Latch (WEL) is reset on power-

•A Write Enable (

WREN) instruction must be issued

to set the write enable latch

• After a write, ERAL, SETAL, or WRSR command,

the write enable latch is reset

• Commands to access the array or write to the

status register are ignored during an internal write

cycle and programming is not affected

6.0 POWER-ON STATE

The 11XX powers on in the following state:

• The device is in low-power Shutdown mode,

requiring a low-to-high transition on SCIO to enter

Idle mode

• The Write Enable Latch (WEL) is reset

• The internal Address Pointer is undefined

• A low-to-high transition, standby pulse and subse-

quent high-to-low transition on SCIO (the first low

pulse of the header) are required to enter the

active state

TABLE 6-1: WRITE PROTECT FUNCTIONALITY MATRIX

WEL Protected Blocks Unprotected Blocks Status Register

0 Protected Protected Protected

1 Protected Writable Writable