Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)SOT 23-3 1 kBit 128 x 8

 2011 Microchip Technology Inc. DS22067J-page 1

11AA010/11LC010 11AA080/11LC080

11AA020/11LC020 11AA160/11LC160

11AA040/11LC040 11AA161/11LC161

Features:

• Single I/O, UNI/O

Serial Interface Bus

• Low-Power CMOS Technology:

- 1 mA active current, typical

- 1 µA standby current (max.) (I-temp)

• 128 x 8 through 2,048 x 8 Bit Organizations

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kbps Max. Bit Rate – Equivalent to 100 kHz

Clock Frequency

• Self-Timed Write Cycle (including Auto-Erase)

• Page-Write Buffer for up to 16 Bytes

• STATUS Register for Added Control:

- Write enable latch bit

- Write-In-Progress bit

• Block Write Protection:

- Protect none, 1/4, 1/2 or all of array

• Built-in Write Protection:

- Power-on/off data protection circuitry

- Write enable latch

• High Reliability:

- Endurance: 1,000,000 erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4,000V

• 3-lead SOT-23 and TO-92 Packages

• 4-lead Chip Scale Package

• 8-lead PDIP, SOIC, MSOP, TDFN Packages

• Pb-Free and RoHS Compliant

• Available Temperature Ranges:

Pin Function Table

Description:

The Microchip Technology Inc. 11AAXXX/11LCXXX

(11XX

) devices are a family of 1 Kbit through 16 Kbit

Serial Electrically Erasable PROMs. The devices are

organized in blocks of x8-bit memory and support the

patented** single I/O UNI/O

serial bus. By using

Manchester encoding techniques, the clock and data

are combined into a single, serial bit stream (SCIO),

where the clock signal is extracted by the receiver to

correctly decode the timing and value of each bit.

Low-voltage design permits operation down to 1.8V (for

11AAXXX devices), with standby and active currents of

only 1 uA and 1 mA, respectively.

The 11XX family is available in standard packages

including 8-lead PDIP and SOIC, and advanced pack-

aging including 3-lead SOT-23, 3-lead TO-92, 4-lead

Chip Scale, 8-lead TDFN, and 8-lead MSOP.

Package Types (not to scale)

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Name Function

SCIO Serial Clock, Data Input/Output

SS Ground

CC Supply Voltage

Vss

VCC

SCIO

PDIP/SOIC

(P, SN)

VCC

SCIO

(MS)

TDFN

SCIO

VCC

(MN)

MSOP

SOT23

SCIO

VSS

(TT)

Vcc

TO-92

SCIO

(TO)

VSS

SCIO

(Top down view,

balls not visible

)

Note 1: Available in I-temp, “AA” only.

Vss

CS (Chip Scale)

(1)

1K-16K UNI/O

Serial EEPROM Family Data Sheet

* 11XX is used in this document as a generic part number for the 11 series devices.

** Microchip’s UNI/O

Bus products are covered by some or all of the following patents issued in the U.S.A.: 7,376,020 & 7,788,430.

Summary of content (48 pages)

PAGE 1
1AA010/11LC010 11AA020/11LC020 11AA040/11LC040 11AA080/11LC080 11AA160/11LC160 11AA161/11LC161 1K-16K UNI/O® Serial EEPROM Family Data Sheet Features: Description: • Single I/O, UNI/O® Serial Interface Bus • Low-Power CMOS Technology: - 1 mA active current, typical - 1 µA standby current (max.) (I-temp) • 128 x 8 through 2,048 x 8 Bit Organizations • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kbps Max.
PAGE 2
11XX DEVICE SELECTION TABLE Part Number Density Organization VCC Range (bits) Page Size (Bytes) Temp. Ranges Device Address Packages 11LC010 1K 128 x 8 2.5-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT 11AA010 1K 128 x 8 1.8-5.5V 16 I 0xA0 P, SN, MS, MN, TO, TT, CS 11LC020 2K 256 x 8 2.5-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT 11AA020 2K 256 x 8 1.8-5.5V 16 I 0xA0 P, SN, MS, MN, TO, TT, CS 11LC040 4K 512 x 8 2.5-5.
PAGE 3
11XX 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V SCIO w.r.t. VSS .....................................................................................................................................-0.6V to VCC+1.0V Storage temperature .............................................................................
PAGE 4
11XX TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = 2.5V to 5.5V VCC = 1.8V to 2.5V Automotive (E): VCC = 2.5V to 5.5V AC CHARACTERISTICS Param. No. Sym. Characteristic 1 FBUS 2 TE Min. Max. Units Serial bus frequency 10 100 kHz — Bit period 10 100 µs — Input edge jitter tolerance — ±0.06 UI (Note 3) FDRIFT Serial bus frequency drift rate tolerance — ±0.
PAGE 5
11XX FIGURE 1-1: 10 BUS TIMING – START HEADER 11 2 SCIO Data ‘0’ FIGURE 1-2: Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit BUS TIMING – DATA 2 7 8 Data ‘1’ Data ‘0’ 12 SCIO Data ‘0’ FIGURE 1-3: Data ‘1’ Data ‘1’ BUS TIMING – STANDBY PULSE 9 SCIO Standby Mode FIGURE 1-4: BUS TIMING – JITTER 2 3 Ideal Edge from Master  2011 Microchip Technology Inc.
PAGE 6
11XX 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 11XX family of serial EEPROMs support the UNI/O® protocol. They can be interfaced with microcontrollers, including Microchip’s PIC® microcontrollers, ASICs, or any other device with an available discrete I/O line that can be configured properly to match the UNI/O protocol. The 11XX devices contain an 8-bit instruction register. The devices are accessed via the SCIO pin.
PAGE 7
11XX 3.0 BUS CHARACTERISTICS 3.1 Standby Pulse If a command is terminated in any manner other than a NoMAK/SAK combination, then the master must perform a standby pulse before beginning a new command, regardless of which device is to be selected. When the master has control of SCIO, a standby pulse can be generated by holding SCIO high for TSTBY. At this time, the 11XX will reset and return to Standby mode.
PAGE 8
11XX 3.3 FIGURE 3-4: Acknowledge MAK (‘1’) SAK (‘1’) NoMAK (‘0’) NoSAK(1) An Acknowledge routine occurs after each byte is transmitted, including the start header. This routine consists of two bits. The first bit is transmitted by the master, and the second bit is transmitted by the slave. Note: A MAK must always be transmitted following the start header. The Master Acknowledge, or MAK, is signified by transmitting a ‘1’, and informs the slave that the current operation is to be continued.
PAGE 9
11XX 3.6 Device Standby The 11XX features a low-power Standby mode during which the device is waiting to begin a new command. A high-to-low transition on SCIO will exit low-power mode and prepare the device for receiving the start header. Standby mode will be entered upon the following conditions: • A NoMAK followed by a SAK (i.e.
PAGE 10
11XX 4.0 DEVICE COMMANDS After the device address byte, a command byte must be sent by the master to indicate the type of operation to be performed. The code for each instruction is listed in Table 4-1.
PAGE 11
XX 4.2 TABLE 4-2: Current Address Read (CRRD) Instruction The internal address counter featured on the 11XX maintains the address of the last memory array location accessed. The CRRD instruction allows the master to read data back beginning from this current location. Consequently, no word address is provided upon issuing this command.
PAGE 12
11XX Write Instruction Prior to any attempt to write data to the 11XX, the write enable latch must be set by issuing the WREN instruction (see Section 4.4 “Write Enable (WREN) and Write Disable (WRDI) Instructions”). Once the write enable latch is set, the user may proceed with issuing a WRITE instruction (including the header and device address bytes) followed by the MSB and LSB of the Word Address. Once the last Acknowledge sequence has been performed, the master transmits the data byte to be written.
PAGE 13
11XX Write Enable (WREN) and Write Disable (WRDI) Instructions The 11XX contains a write enable latch. See Table 6-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI instruction will reset the latch. Note: The WREN and WRDI instructions must be terminated with a NoMAK following the command byte.
PAGE 14
11XX 4.5 Read Status Register (RDSR) Instruction The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user through the WRSR instruction. These bits are nonvolatile. The RDSR instruction provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle.
PAGE 15
11XX Write Status Register (WRSR) Instruction After transmitting the STATUS register data, the master must transmit a NoMAK during the Acknowledge sequence in order to initiate the internal write cycle. The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array.
PAGE 16
11XX Erase All (ERAL) Instruction The ERAL instruction allows the user to write ‘0x00’ to the entire memory array with one command. Note that the write enable latch (WEL) must first be set by issuing the WREN instruction. Once the write enable latch is set, the user may proceed with issuing a ERAL instruction (including the header and device address bytes).
PAGE 17
11XX 5.0 DATA PROTECTION The following protection has been implemented to prevent inadvertent writes to the array: • The Write Enable Latch (WEL) is reset on powerup • A Write Enable (WREN) instruction must be issued to set the write enable latch • After a write, ERAL, SETAL, or WRSR command, the write enable latch is reset • Commands to access the array or write to the status register are ignored during an internal write cycle and programming is not affected 6.
PAGE 18
11XX 7.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 7-1. TABLE 7-1: PIN FUNCTION TABLE 3-pin SOT-23 3-pin TO-92 4-pin CS 8-pin PDIP/SOIC/ MSOP/TDFN SCIO 1 2 3 5 Serial Clock, Data Input/Output VCC 2 3 1 8 Supply Voltage VSS 3 1 2 4 Ground NC — — 4 1,2,3,6,7 Name 7.
PAGE 19
11XX 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 11AA160 I/P e3 1L7 0828 8-Lead PDIP Package Marking (Pb-Free) Note: Device Line 1 Marking Device Line 1 Marking 11AA010 11AA010 11LC010 11LC010 11AA020 11AA020 11LC020 11LC020 11AA040 11AA040 11LC040 11LC040 11AA080 11AA080 11LC080 11LC080 11AA160 11AA160 11LC160 11LC160 11AA161 11AA161 11LC161 11LC161 T = Temperature Grade (I, E) Legend: XX...
PAGE 20
11XX 8-Lead SOIC Example: XXXXXXXT XXXXYYWW NNN 11AA160I SN e3 0828 1L7 8-Lead SOIC Package Marking (Pb-Free) Note: Device Line 1 Marking Device Line 1 Marking 11AA010 11AA010T 11LC010 11LC010T 11AA020 11AA020T 11LC020 11LC020T 11AA040 11AA040T 11LC040 11LC040T 11AA080 11AA080T 11LC080 11LC080T 11AA160 11AA160T 11LC160 11LC160T 11AA161 11AA161T 11LC161 11LC161T T = Temperature Grade (I, E) Legend: XX...
PAGE 21
11XX 8-Lead MSOP (150 mil) XXXXXXT YWWNNN Example: 11A01I e3 8281L7 8-Lead MSOP Package Marking (Pb-Free) Note: Device Line 1 Marking Device Line 1 Marking 11AA010 11A01T 11LC010 11L01T 11AA020 11A02T 11LC020 11L02T 11AA040 11A04T 11LC040 11L04T 11AA080 11A08T 11LC080 11L08T 11AA160 11AAT 11LC160 11LAT 11AA161 11AA1T 11LC161 11LA1T T = Temperature Grade (I, E) Legend: XX...
PAGE 22
11XX 8-Lead 2x3 TDFN Example: XXX YWW NN D51 828 17 8-Lead 2x3 TDFN Package Marking (Pb-Free) Device I-Temp Marking Device I-Temp Marking E-Temp Marking 11AA010 D11 11LC010 D14 D15 11AA020 D21 11LC020 D24 D25 11AA040 D31 11LC040 D34 D35 11AA080 D41 11LC080 D44 D45 11AA160 D51 11LC160 D54 D55 11AA161 D5D 11LC161 D5G D5H Legend: XX...
PAGE 23
11XX 3-Lead SOT-23 Example: XXNN B517 3-Lead SOT-23 Package Marking (Pb-Free) Device I-Temp Marking Device I-Temp Marking E-Temp Marking 11AA010 B1NN 11LC010 M1NN N1NN 11AA020 B2NN 11LC020 M2NN N2NN 11AA040 B3NN 11LC040 M3NN N3NN 11AA080 B4NN 11LC080 M4NN N4NN 11AA160 B5NN 11LC160 M5NN N5NN 11AA161 B0NN 11LC161 M0NN N0NN Legend: XX...
PAGE 24
11XX 3-Lead TO-92 XXXXXX T/XXXX YWW NNN Example: 11A160 e3 e3 I/TO 928 1L7 3-Lead TO-92 Package Marking (Pb-Free) Note: Device Line 1 Marking Device Line 1 Marking 11AA010 11A010 11LC010 11L010 11AA020 11A020 11LC020 11L020 11AA040 11A040 11LC040 11L040 11AA080 11A080 11LC080 11L080 11AA160 11A160 11LC160 11L160 11AA161 11A161 11LC161 11L161 T = Temperature Grade (I, E) Legend: XX...
PAGE 25
11XX 4-Lead Chip Scale Example: XW NN E3 17 4-Lead Chip Scale Package Marking (Pb-Free) Device Legend: XX...X Y YY WW NNN e3 * Note: Line 1 Marking 11AA010 AW 11AA020 BW 11AA040 CW 11AA080 DW 11AA160 EW 11AA161 HW Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
PAGE 26
11XX 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; < & & 7: 1 , = = - 1 ! & & = = .
PAGE 27
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc.
PAGE 28
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22067J-page 28  2011 Microchip Technology Inc.
PAGE 29
11XX ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4  2011 Microchip Technology Inc.
PAGE 30
11XX ( " ! ) * ( ( ! 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = < = # # 4 4 !! & # %% ? 1 , : > #& . # # 4 > #& .
PAGE 31
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc.
PAGE 32
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22067J-page 32  2011 Microchip Technology Inc.
PAGE 33
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc.
PAGE 34
11XX + $ ) * ( ,- - %./ 0 + 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS22067J-page 34  2011 Microchip Technology Inc.
PAGE 35
11XX 0" " ! 0! 0! &, 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 E A N 1 L 1 2 3 b e c D R 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 ; - & 1 && ' & 4 3 & ? : > #& .
PAGE 36
11XX ! 0" " 00 !0 , 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 b N E E1 2 1 e e1 D c A φ A2 A1 L 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7: ; 7 - 9 # & 1 , :"&! # 9 # & : 8 & < = = # # 4 4 !! & # %% 1 , : > #& .
PAGE 37
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc.
PAGE 38
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22067J-page 38  2011 Microchip Technology Inc.
PAGE 39
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc.
PAGE 40
11XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22067J-page 40  2011 Microchip Technology Inc.
PAGE 41
11XX APPENDIX A: REVISION HISTORY Revision A (10/07) Original release of this document. Revision B (01/08) Revised SOT-23 Package Type; Revised DFN package to TDFN; Section 3.3 (added new bullet item); Section 4.5 note; Table 7-1. Revision C (03/08) Removed patent pending notice; Revised Tables 1-1 and 1-2; Section 3.3 (bullet 3) and 3.7 (bullet 2); Product ID System. Revision D (04/08) Revised document status to Preliminary; General updates.
PAGE 42
11XX NOTES: DS22067J-page 42  2011 Microchip Technology Inc.
PAGE 43
11AAXXX/11LCXXX THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 44
11AAXXX/11LCXXX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 45
11AAXXX/11LCXXX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X PART NO. Device X X /XXX Device Tape & Reel Temperature Package Address Range Examples: a) b) Device: 11AA01 = 11LC01 = 11AA02 = 11LC02 = 11AA04 = 11LC04 = 11AA08 = 11LC08 = 11AA16 = 11LC16 = Device Address: 0 1 Tape & Reel: T Blank 1 Kbit, 1.8V UNI/O Serial EEPROM 1 Kbit, 2.5V UNI/O Serial EEPROM 2 Kbit, 1.
PAGE 46
11AAXXX/11LCXXX NOTES: DS22067J-page 46 Preliminary  2011 Microchip Technology Inc.
PAGE 47
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 48
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