Specifications

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Global Registers (Continued)
Address Name Description Mode Default
3 Enable PHY MII/RMII
1, enable PHY P5-MII/RMII interface (default).
Note: if not enabled, the switch will tri-state all outputs.
R/W
1
Pin LED[5][1]
strap option.
PD(0): isolate.
PU(1): Enable.
Note: LED[5][1]
has internal pull-
up (PU).
2 Reserved N/A Do not change. RO 1
1 UNH Mode
1, the switch will drop packets with 0x8808 in T/L filed,
or DA = 01-80-C2-00-00-01.
0, the switch will drop packets qualified as “flow control”
packets.
R/W 0
0 Link Change Age
1, link change from “link” to “no link” will cause fast
aging (<800µs) to age address table faster. After an
age cycle is complete, the age logic will return to
normal (300 +/- 75 seconds ). Note: If any port is
unplugged, all addresses will be automatically aged
out.
R/W 0
Register 3 (0x03): Global Control 1
7 Pass All Frames
1, switch all packets including bad ones. Used solely
for debugging purpose. Works in conjunction with
sniffer mode.
R/W 0
6 2K Byte packet support
1 = enable support 2K Byte packet
0 = disable support 2K Byte packet
R/W 0
5
IEEE 802.3x Transmit
Flow Control Disable
0, will enable transmit flow control based on AN result.
1, will not enable transmit flow control regardless of
AN result.
R/W
0
Pin PMRXD3
strap option.
PD(0): Enable Tx
flow control
(default).
PU(1): Disable
Tx/Rx flow
control.
Note: PMRXD3
has internal pull-
down.
4
IEEE 802.3x Receive
Flow Control Disable
0, will enable receive flow control based on AN result.
1, will not enable receive flow control regardless of
AN result.
Note: Bit 5 and bit 4 default values are controlled by
the same pin, but they can be programmed
independently.
R/W
0
Pin PMRXD3
strap option.
PD (0): Enable
Rx flow control
(default).
PU(1): Disable
Tx/Rx flow
control.
Note: PMRXD3
has internal pull-
down.
March 12, 2014
57
Revision 1.7