Specifications
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Global Registers
Address Name Description Mode Default
Register 0 (0x00): Chip ID0
7−0
Family ID Chip family. RO 0x95
Register 1 (0x01): Chip ID1 / Start Switch
7−4
Chip ID
0100 = KSZ8895MQ/FMQ
0110 = KSZ8995RQ
RO
0x4 is for
MQ/FMQ
0x6 is RQ
3−1
Revision ID Revision ID RO 0x0
0 Start Switch
1, start the chip when external pins (PS1, PS0) = (1,0)
Note: in (PS1,PS0) = (0,0) mode, the chip will
start automatically, after trying to read the external
EEPROM. If EEPROM does not exist, the chip will use
default values for all internal registers. If EEPROM is
present, the contents in the EEPROM will be checked.
The switch will check:
7 Register 0 = 0x95,
(2) Register 1 [7:4] = Availible chip ID.
If this check is OK, the contents in the EEPROM will
override chip register default values =0, chip will not
start when external pins
(PS1, PS0) = (1,0) or (0,1).
Note: (PS1, PS0) = (1,1) for Factory test only.
0, stop the switch function of the chip.
R/W
0
Register 2 (0x02): Global Control 0
7 New Back-off Enable
New Back-off algorithm designed for UNH
1 = Enable
0 = Disable
R/W 0
6 Reserved Reserved. RO 0
5 Flush dynamic MAC table
Flush the entire dynamic MAC table for RSTP
1 = Trigger the flush dynamic MAC table operation.
This bit is self clear
0 = normal operation
Note: All the entries associated with a port that has its
learning capability being turned off (Learning Disable)
will be flushed. If you want to flush the entire Table, all
ports learning capability must be turned off.
R/W
(SC)
0
4 Flush static MAC table
Flush the matched entries in static MAC table for RSTP
1 = Trigger the flush static MAC table operation. This
bit is self clear
0 = normal operation
Note: The matched entry is defined as the entry whose
Forwarding Ports field contains a single port and MAC
address with unicast. This port, in turn, has its learning
capability being turned off (Learning Disable). Per port,
multiple entries can be qualified as matched entries.
R/W
(SC)
0
March 12, 2014
56
Revision 1.7