Specifications

Micrel, Inc.

KSZ8895MQ/RQ/FMQ

MII Interface Operation

The media-independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface

between physical layer and MAC layer devices. The KSZ8895MQ/RQ/FMQ provides two such interfaces. The P5-MII

interface is used to connect to the fifth PHY, where as the SW-MII interface is used to connect to the fifth MAC. Each

of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving.

Port 5 PHY 5 P5-MII/RMII Interface

The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface

between the physical layer and MAC layer devices. The Reduced Media Independent Interface (RMII) specifies a low

pin count MII. The KSZ8895MQ/RQ/FMQ provides two such interfaces for MAC5 and PHY5. The Port 5 PHY5 P5-

MII/RMII interface is used to connect to the fifth PHY, where as the SW-MII/RMII interface is used to connect to the

fifth MAC. The KSZ8895MQ/FMQ support P5-MII, the KSZ8895RQ supports P5-RMII. Each of these MII/RMII

interfaces contains two distinct groups of signals, one for transmission and the other for receiving. Table 3 describes

the signals used in the PHY[5] P5-MII/RMII interface. The P5-MII interface operates in PHY mode only.

MII

Signal

Description

KSZ8895MQ/FMQ

P5-MII

KSZ8895MQ/FMQ

MII Signal Type

KSZ8895RQ

P5-RMII

KSZ8895RQ

RMII Signal

Type

MTXEN Transmit enable PMTXEN I PMTXEN I

MTXER Transmit error PMTXER I

MTXD3 Transmit data bit 3 PMTXD[3] I

MTXD2 Transmit data bit 2 PMTXD[2] I

MTXD1 Transmit data bit 1 PMTXD[1] I PMTXD[1] I

MTXD0 Transmit data bit 0 PMTXD[0] I PMTXD[0] I

MTXC Transmit clock PMTXC O PMREFCLK/PMTXC I

MCOL Collision detection PCOL O

MCRS Carrier sense PCRS O

MRXDV Receive data valid PMRXDV O PMRXDV O

MRXER Receive error PMRXER O PMRXER O

MRXD3 Receive data bit 3 PMRXD[3] O

MRXD2 Receive data bit 2 PMRXD[2] O

MRXD1 Receive data bit 1 PMRXD[1] O PMRXD[1] O

MRXD0 Receive data bit 0 PMRXD[0] O PMRXD[0] O

MRXC Receive clock PMRXC O PMRXC O

Table 3. Port 5 PHY P5-MII/RMII Signals

March 12, 2014

Revision 1.7