Specifications
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
64 PMRXD1 IPD/O 5
PHY[5] MII/RMII receive bit 1.
Strap option:
PD (default) = drop excessive collision packets.
PU = does not drop excessive collision packets.
65 PMRXD0 IPD/O 5
PHY[5] MII/RMII receive bit 0.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex
mode.
PU = enable for performance enhancement.
66 PMRXER IPD/O 5
MQ/FMQ:PHY[5] MII receive error
RQ: no connection for RMII
Strap option:
PD (default) = packet size 1518/1522 bytes.
PU = 1536 bytes.
67 PCRS IPD/O 5
MQ/FMQ: PHY[5] MII carrier sense.
RQ: no connection for RMII.
Strap option for port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or
fails.
PU = force full-duplex if auto negotiation is disabled or fails. Refer
to Register 76.
68 PCOL IPD/O 5
MQ/FMQ: PHY[5] MII collision detect.
RQ: no connection.
Strap option for port 4 only.
PD (default) = no force flow control, normal operation.
PU = force flow control. Refer to Register 66.
69 SMTXEN IPD Port 5 Switch MII/RMII transmit enable.
70 SMTXD3 IPD
MQ/FMQ: Port 5 Switch MII transmit bit 3.
RQ: no connection for RMII.
71 SMTXD2 IPD
MQ/FMQ: Port 5 Switch MII transmit bit 2.
RQ: no connection for RMII.
72 SMTXD1 IPD Port 5 Switch MII/RMII transmit bit 1.
73 SMTXD0 IPD Port 5 Switch MII/RMII transmit bit 0.
74 SMTXER IPD
MQ/FMQ: Port 5 Switch MII transmit error.
RQ: no connection for RMII.
75
SMTXC/SMREFCLK
I/O
MQ/FMQ: Port 5 Switch MII transmit clock,
Input: SW5-MII MAC mode, Output: SW5-MII PHY modes.
RQ: Input SW5-RMII 50MHz +/-50ppm reference clock. The
50MHz clock comes from SMRXC Pin 78 when the device is the
clock mode which the device’s clock comes from 25MHz
crystal/oscillator from pins X1/X2. Or the 50MHz clock comes
from external 50MHz clock source when the device is the normal
mode which the device’s clock source comes from SMTXC pin
not from X1/X2 pins.
76 GNDD GND Digital ground.
77 VDDIO P 3.3V, 2.5V or 1.8V digital V
DD
for digital I/O circuitry.
March 12, 2014
18
Revision 1.7