Specifications

OPERATIONAL TIMING

Summary of Operation Timings

Operation Timing Specifications

Parameter Description Typical

Tprw_up

Power Applied to Processor Ready Delay

(USB)

9 Seconds

Tprw_up_ttl

Trigger or Wake Low to Processor Ready

Delay (TTL)

TBD

Tdec_idle

Trigger Low to Decode complete Delay

(Note 1 and 2)

90msec

Tdec_sleep

Trigger Low to Decode complete Delay

(Note 1 and 3)

120msec

Trig_min Minimum duration of trigger signal 20msec

Note 1

Timing is the Same for Both TTL or USB version

Note 2

Processor is in Idle state when Trigger signal received

Note 3

Processor is in Sleep state when Trigger signal received