User's Manual

Test Pattern File Formats FlexTest Test Pattern File Format
FastScan and FlexTest Reference Manual, V8.6_4
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VCD Support Using VCD Plus
FlexTest accepts existing Verilog or VHDL functional patterns through its VCD
(Value Change Dump) Plus files which can be generated during simulation. This
functionality is useful because FlexTest can use existing functional patterns to get
some initial fault coverage, and then perform ATPG on the remaining faults. This
can result in smaller test pattern sets and shorter run times. Also due to that fact
that the FlexTest fault simulation engine doesn’t consider timing, FlexTest fault
simulation should be faster than other fault simulators.
This feature mainly contains two tasks:
• Parsing a VCD Plus file.
• Converting the event based patterns in the VCD file to cycle based vectors
stored in FlexTest internal pattern data structure which can be used by the
cycle based FlexTest fault simulation engine to perform fault simulation.
The VCD Plus format that is supported is the LSI Logic’s extended VCD format.
Comparing with the standard VCD format, the extended VCD format provides
sufficient simulation information on bidirectional signals -- driving direction,
driving strength and collision detection. For more detailed information about LSI
Logic’s extended VCD format and the methods of generating it from various
simulators, contact LSI Logic and the respective EDA vendor.
To create a VCD Plus file for a VHDL or Verilog design from ModelSim EE/Plus
(using version 5.1e or later), use the following ModelSim commands:
vcd file filename.vcd -dumpports
vcd add -r