User`s guide

10
The paged memory map structure of the MTX computers was designed to operate in two modes :-
1. ROM Based (RELCPM = 0)
ROMs are mapped from 0 to 3FFFh. The 8K (2000h bytes) monitor ROM is always available in area 0
to 1FFFh and the paged ROMs of 8K (2000h bytes) each are mapped from 2000h to 3fffh as eight
pages 0 to 7 set by R2,R1,R0 in the page port write only register. Up to 512K of RAM is mapped on
16 pages (0 to F) set up by P3,P2,P1 and P0 in the page port write only register. The area C000h to
FFFFh is a 16K (4000h bytes) block common to all RAM pages. The 32K (8000h bytes) block from
4000h to BFFFh is mapped as 16 pages. The 32K bytes of RAM for an MTX500 is mapped from
8000h to FFFFh (page 0). The 64K bytes of RAM for an MTX512 is mapped from 4000h to FFFFh
(page 0). The additional 16K is mapped from 8000h to C000h on page 1.
2. RAM Based (RELCPM = 1)
All ROMs are switched out in this mode and up to 16 pages of 48K (C000h bytes) are mapped from 0
to BFFFh. These pages are set by P3, P2, P1 and P0 in the page port write only register. In the area
C000h to FFFFh is a 16K block (4000h bytes) of RAM common to all pages.
MEMORY MAP PICTURES
Default MTX ROM Based Memory Map, RELCPM = 0
R2,R1,R0 0x0000..0x1fff 0x2000..0x3fff 0x4000..0x7fff 0x8000..0xbfff 0xc000..0xffff
0
MONITOR
A
(OS)
SYS B (BASIC) 512 500 / 512 500/512
4000h
Bytes
Common
Block
1
SYS C (ASSEM) (128a) 512
2
(128c) (128b)
3
(128e) (128d)
4
CP/M boot ROM (128g) (128f)
5
SDX ROM (128h)
6
7
CARTRIDGE
R2, R1, R0
(128K Add-on to
MTX512 shown
in brackets (a-h))