Service manual

11
Pin Description
CE.
Chip Enable (input, active Low). When enabled the
CTC accepts control words, interrupt vectors, or
time constant data words from the data bus during
an I/O write cycle; or transmits the contents of
the down-counter to the CPU during an I/O read
cycle. In most applications this signal is
decoded from the eight least significant-bits of
the address bus for any of the four I/O port
addresses that are mapped to the four counter-
timer channels.
CLK.
System Clock (input). Standard Single-phase Z-80
system clock.
CLK/TRG0-CLK/TRG3.
External Clock/Timer Trigger (input, user-
selectable active High or Low). Four pins
corresponding to the four Z-80 CTC channels. In
counter mode, every active edge on this pin
decrements the down-counter. In timer mode, an
active edge starts the timer.
CS0-CS1.
Channel Select (inputs active High). Two-bit
binary address code selects one of the four CTC
channels for an I/O write or read (usually
connected to A0 and A1).
D0-D7.
System Data Bus (bidirectional, 3-state).
Transfers all data and commands between the Z-80
CPU and the Z-80 CTC.
IEI.
Interrupt Enable In (input, active High). A High
indicates that no other interrupting devices of
higher priority in the daisy chain are being
serviced by the Z-80 CPU.
IEO.
Interrupt Enable Out (output, active High). High
only if IEI is High and the Z-80 CPU is not
servicing an interrupt from any Z-80 CTC channel.
IEO blocks lower priority devices from
interrupting while a higher priority interrupting
device is being serviced.
MTX Service Manual