Datasheet

Copy # The twin-card option is not supported.
Socket # The socket number is ignored.
Memory and I/O Modes Decoding
Memory Mode Decoding
Memory mode allows hosts to access ATA registers within a 2-Kbyte contiguous memory space.
The first 16 bytes contain ATA task-file registers. Offsets 400h-7FFh provide alternate ATA data
register addresses. The host must decode memory addresses A11 and above to provide card-enables
CE1# and CE2#. The drive decodes addresses A0-10. The flash drive is in memory mode at
power-on or card insertion or when the host writes configuration index value 00h to the card’s
Configuration Option register. Table 8 summarizes the memory-mode ATA task file registers.
Register Offset Register Offset
Data 000h Data Low (duplicate) 008h
Error (read), Set Feature (write) 001h Data High (duplicate) 009h
Sector Count 002h Not Used 00Ah-00Ch
Sector Number 003h Error (duplicate) 00Dh
Cylinder Low 004h Alternate Status (read) 00Eh
Cylinder High 005h Drive Control (write)
Drive/Head 006h Drive Address 00Fh
Status (read), Command (write) 007h Data (duplicate) 400h-7FFh
Table 8. Memory-mode Task-file Registers
8-bit-only hosts have trouble independently accessing the 16-bit data register’s low and high bytes.
Normally, an 8-bit host would access offset 000h for the low byte and 001h for the high byte.
However, in ATA implementations, offset 001h is the error register. PCMCIA’s PC Card ATA
specification provides an alternate addressing scheme that solves this problem. The data register can
be accessed at either offset 000h, 008h, 009h, or between offsets 400h-7FFh. The error register can
be accesses at either offset 001h or 00Dh.
Offset 000h and 008h operate identically. In 8-bit mode (CE1# asserted, CE2# de-asserted, A0 = 0),
each 000h- or 008h- offset access presents sequential data bytes over D0-7. The first access presents
a data-word’s low byte, the next access presents the word’s high byte. Offset 000h accesses with
CE1# de-asserted and CE2# asserted present Error register contents over D8-15. In 16-bit mode
(CE1# and CE2# asserted, A0 = don’t care), each offset 000h or 008h access presents sequential
data words on D0-15.
Offset 009h allows an 8-bit host to access the data register’s high-byte over D0-7. The drive
presents low-then-high bytes if a host repeatedly accesses offset 008h followed by 009h. The drive
presents high-then-low bytes if a host repeatedly accesses offset 009h followed by 008h. Sequential
high-byte access at 009h are not supported.