Datasheet

registers are located on even-byte attribute-plane addresses to ensure access in 8- and 16-bit
system. Available card status information allows arbitration between resources that share
interrupts and status of memory-only-card pins 16, 33, 62, and 63.
Register
Add. Offset
1
R/W REG# CE2# CE1# OE# WE# D15-8 D7-0
Configuration 200h Read L H L L H Invalid Option
Option Write L H L H L Invalid Option
Card Configuration 202h
2
Read L H L L H Invalid Status
and Status Write L H L H L Invalid Config
Pin Replacement 202h
2
Read L H L L H Invalid Pin Status
Write L H L H L Invalid Pin Status
Socket and Copy 202h
2
Read L H L L H Invalid Socket ID
Write L H L H L Invalid Socket ID
Notes
1 The host obtains attribute-memory address offset from the Configuration Tuple’s tpcc_radr field when it
reads the drive’s CIS.
2 Some engineering samples (marked ES) and early production units do not support these registers.
Configuration Option Register
The host uses the read/write Configuration Option register to configure the drive for drive for one
of its four PCMCIA-ATA addressing modes, establish the interrupt signal mode, and issue a soft
reset.
7 6 5 4 3 2 1 0
SRST IRQLvl Configuration Index
SRST Resets the card when 1. When 0 (default) after a hardware or software reset or
power-on, the card is unconfigured. A configuration occurs when a valid configuration
index is written to bits 0-5.
IRQLvl Selects level mode interrupts when 1, pulse mode interrupts when 0 (default).
Conf IDX The host chooses an option from the card’s configuration table entry tuples and writes
that option’s Configuration Index number into this field. When zero (default), the
memory-only interface is chosen, I/O accesses are disabled.
Configuration & Status Register
The Configuration and Status register contains card condition information.
7 6 5 4 3 2 1 0
Chng SigChg Iois8 0 Audio PwrDn Intr 0
Chng The Change bit indicates that a Pin Replacement register bit was changed.