Specifications

13
Finally Flash
The development of flash memory solved the problem of slow one-byte-at-a-time erasure of the
EEPROMs by using in-circuit wiring across the chip so that either the entire chip could be erased
or only selected sections known as blocks. Writing to the chip is also faster because data can
transfer at a rate of 512-byte sections instead of the EEPROMs’ slower individual bytes. The links
are much the same design as those in EPROMS and EEPROMs— floating gate/oxide layer/control
gates. Figure 4 shows a connected link that allows electricity (the yellow arrow) to flow through the
floating gate, the thin oxide layer, and the control gate at a rate of at least 50% of the intended
current. As long as the current flow is above 50%, the link is in place and the intersection has a
value of 1.
Figure 5 shows the same link with a 10-13 volt charge (the black arrow) applied to the floating gate
transistor that forces electron blockers through the thin oxide layer to its other side. The electrons
reduce current flow (the yellow arrow) to the control gate to less than half its value, and that
effectively makes this intersection a 0 in binary terms because the link is no longer recognized. In
order to restore the flow of current through the control gate and change the value of the link back to
a 1, a higher voltage field is applied to remove the electron blockers. Figure 6 is a comparison
chart listing the various types of memory chips with their advantages and disadvantages.
SLC and MLC
There are two types of cells known as single level cells (SLC) and multi-level cells (MLC). In order to reduce
the cost of memory, designers developed a more complex MLC design that doubles the amount of memory
on a single chip. The simpler, more expensive SLC uses one bit of data for each cell and holds that bit in
one of two states: “1” for erased or “0” for programmed. The MLC design stores 2 bits in each cell in one of
four possible states: “11” for erased, “10” for two thirds, “01” for one third, or “00” for programmed. MLC
designs have a clear advantage in terms of density and lower cost of manufacturing, but their complexity
necessitates more error checking. The enhanced EDC (error detection and correction) eats up part of the
storage capacity MLC gains, and the extra complexity slows the memory chips down considerably. Simpler
SLC chips can write up to three times faster than MLC chips and read over 40% faster. Durability tests
suggest that SLC chips may also be more reliable than MLC chips. One study showed SLC chips capable of
100,000 read/write cycles compared to MLC’s 10,000 cycles. Certain requirements for faster read/write
cycles, such as Windows® ReadyBoost™, have lead to dual-channel MLC chips that are much faster than
single MLC memory chips and competitive with SLC in terms of speed.
Figure 4