User Manual

Application Note
SMBus communication with MLX90614
390119061402 Page 8 of 32 Jan-2008
Rev 004
specifications are an alternative to the lower power specifications stated above and may be
used in environments where necessary.
Table 3
Symbol Parameter Min Max Units Comments
V
IL
SMBus signal Input low voltage - 0.8 V
V
IH
SMBus signal Input high voltage 2.1 V
DD
V
V
OL
SMBus signal Output low voltage - 0.4 V @ I
PULLUP
I
LEAK-BUS
Input Leakage per bus segment ±200
µA
I
LEAK-PIN
Input Leakage per device pin ±10
µA
V
DD
Nominal bus voltage 2.7 5.5 V
3V to 5V ±10%
I
PULLUP
Current sinking, V
OL
=0.4V 4 mA
C
BUS
Capacitive load per bus segment 400 pF Note 1
C
I
Capacitance for SDA or SCL pin 10 pF Note 2
V
NOISE
Signal noise immunity from
10MHz to 100MHz
300 - mVp-p This AC item applies
To the high-power DC
Specification only
Note 1: Capacitive load for each bus line includes all pin, wire and connector capacitances. The maximum
capacitive load affects the selection of the R
PU
pull-up resistor or the current source in order to meet the rise time
specifications of SMBus.
Note 2: Pin capacitance (C
I
) is defined as the total capacitive load of one SMBus device as seen in a typical
manufacturer's data sheet.
While SMBus devices used in low-power segments have practically no minimum current sinking
requirements due to the low pull-up current specified for low-power segments, devices in high-
power segments are required to sink a minimum current of 4 mA while maintaining the V
OL,MAX
of
0.4 Volts. The requirement for 4 mA sink current determines the minimum value of the pull-up
resistor R
PU
that can be used in SMBus systems.
Unpowered devices connected to either a low-power or high-power SMBus segment must
provide, either within the device or through the interface circuitry, protection against “back
powering” the SMBus.
4.9 Bit transfer
In accordance to the SMBus specification, the MSb is transferred first. SMBus uses fixed voltage
levels to define the logic “ZERO” and logic “ONE” on the bus respectively. The data on SDA
must be stable during the “HIGH” period of the clock. Data can change state only when SCL is
low. Each transfer begins with START bit and finishes with STOP bit (Fig.6).
Fig.6: SMBus byte format
START bit is defined by HIGH to LOW transition of the SDA line while SCL is HIGH. STOP bit is
defined by LOW to HIGH transition of the SDA line while SCL is HIGH. Every byte consists of 8
bits. Each byte transferred on the bus must be followed by an acknowledge bit. The
acknowledge-related clock pulse is generated by the master (ACK clock). The transmitter,
master or slave, releases the SDA line (HIGH) during the acknowledge clock cycle. In order to