User Manual

Application Note
SMBus communication with MLX90614
390119061402 Page 5 of 32 Jan-2008
Rev 004
4.3 Electrical characteristics of SMBus devices
The diagram bellow illustrates the various SMBus timings
Fig.4: SMBus timing measurements
The table below describes all timings.
Table 1
Symbol Parameter Min Max Units Comments
f
SMB
SMBus Operation frequency 10 100 kHz See note 1
t
BUF
Bus free time between Stop and
Start condition
4.7 - µs
t
HD:STA
Hold time after(Repeated)Start
Condition.After this period, the first clock is generated
4.0 - µs
t
SU:STA
Repeated Start Condition setup time 4.7 - µs
t
SU:STO
Stop Condition setup time 4.0 - µs
t
HD:DAT
Data hold time 300 - ns See note 7
t
SU:DAT
Data setup time 250 - ns
t
TIMEOUT
Detect clock low timeout 25 35 ms See note 2
t
LOW
Clock low period 4.7 - µs
t
HIGH
Clock high period 4.0 50 µs See note 3
t
LOW:SEXT
Cumulative clock low extend time
(slave device)
- 25 ms See note 4
t
LOW:MEXT
Cumulative clock low extend time
(master device)
- 10 ms See note 5
t
F
Clock/Data Fall time - 300 ns See note 6
t
R
Clock/Data Rise Time - 1000 ns See note 6
T
POR
Time in which a device must be
Operational after power-on reset
- 500 ms
Note 1: A master shall not drive the clock at a frequency below the minimum f
SMB
. Further, the operating clock
frequency shall not be reduced below the minimum value of f
SMB
due to periodic clock extending by slave devices .
This limit does not apply to the bus idle condition, and this limit is independent from the t
LOW: SEXT
and t
LOW: MEXT
limits. For example, if the SCL is high for t
HIGH,MAX
, the clock must not be periodically stretched longer than
1/f
SMB,MIN
– f
HIGH,MAX
. This requirement does not pertain to a device that extends the SCL low for data processing of a
received byte, data buffering and so forth for longer than 100us in a nonperiodic way.
Note 2: Devices participating in a transfer can abort the transfer in progress and release the bus when any single
clock low interval exceeds the value of t
TIMEOUT,MIN
. After the master in a transaction detects this condition, it must
generate a stop condition within or after the current data byte in the transfer process. Devices that have detected this
condition must reset their communication and be able to receive a new START condition no later than t
TIMEOUT,MAX
.
Typical device examples include the host controller, and embedded controller and most devices that can master the
SMBus. Some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset
its communications port after a start or a stop condition.A timeout condition can only be ensured if the device that is
forcing the timeout holds the SCL low for t
TIMEOUT,MAX
or longer.