User Manual

Application Note
SMBus communication with MLX90614
390119061402 Page 3 of 32 Jan-2008
Rev 004
Devices may be powered by the bus VDD or by another power source Vbus (Fig.1).
Fig.1: SMBus Topology
VDD may be 3 to 5 volts +/- 10% and there may be SMBus devices powered directly by the bus
VDD. Both SDA and SCL lines are bi-directional, connected to a positive supply voltage through
a pull-up resistor or a current source or other similar circuit. When the bus is free, both lines are
high. The output stages of the devices connected to the bus must have an open drain or open
collector in order to perform the wired-AND function. SMBus standard recommends for both the
input and output stages of SMBus devices, not to load the bus when their power plane is turned
off, i.e. powered-down devices should provide no leakage path to ground. A device that wants to
place a ‘zero’ on the bus must drive the bus line to the defined logic low voltage level. In order to
place a logic ‘one’ on the bus the device should release the bus line letting it be pulled high by
the bus pull-up circuitry. The bus lines may be pulled high by a pull-up resistor or by a current
source. In case this involves a higher bus capacitance, a more sophisticated circuit may be used
that can limit the pull-down sink current while also providing enough current during the low-to-
high transition to maintain the rise time specifications of the SMBus.
In SMBus systems with higher bus capacitance (like wires) R
PU
=1.5kΩ (V
DD
=5V,I
PULLUP
=3.3mA)
is suitable otherwise R
PU
=22kΩ(V
DD
=5V,I
PULLUP
=227µA) can be used to meet SMBus low power
DC specification (see low and high power DC specification below).
Version 1.1 of the SMBus specification introduced a Packet Error Checking mechanism to
improve reliability and communication robustness. Implementation of Packet Error Checking by
SMBus devices is optional for SMBus devices. Packet Error Checking, whenever applicable, is
implemented by appending a Packet Error Code (PEC) at the end of each message transfer.
The PEC uses an 8-bit cyclic redundancy check (CRC-8) of each read or write bus transaction
to calculate a Packet Error Code (PEC). The PEC may be calculated in any way that conforms
to a CRC-8 represented by the polynomial, C(x) = x8 + x2 + x1 + 1 and must be calculated in
the order of the bits as received. The PEC calculation includes all bytes in the transmission,
including address, command and data. The PEC calculation does not include ACK, NACK,
START, STOP nor Repeated START bits. This means that the PEC is computed over the entire
message from the first START condition.
For the CRC calculation we use the following procedure:
In the case of the SMBus, the polynomial used is
X8 + X2 + X + 1. The width of this polynomial is 8 (the highest power of X indicates the width)
and it can be represented as 1 0000 0111. Since the width of the polynomial is 8 we refer to
our CRC method as CRC-8.
A message is represented as a bit-stream augmented with M = 8 zeroes at the end.
The augmented bit-stream message is devised by the polynomial 1 0000 0111. The remainder
will be the CRC-8 check byte.