User Manual

Application Note
SMBus communication with MLX90614
390119061402 Page 2 of 32 Jan-2008
Rev 004
4 General SMBus protocol discription
4.1 Definitions of terms
ACK - Acknowledgement from receiver
Address Resolution Protocol - A protocol by which SMBus devices with assignable addresses
on the bus are enumerated and assigned non-conflicting slave addresses.
ASSP - Application Specific Standard Product
Bus Master - Any device that initiates SMBus transactions and drives the clock.
Bus Slave - Target of a SMBus transaction which is driven by some master.
LSb - The Last Significant bit
Master-receiver - A bus master in a SMBus transaction while it is receiving data from a bus
slave during a SMBus transaction.
Master-transmitter - A bus master in a SMBus transaction while it is transmitting data onto the
bus during a SMBus transaction.
MSb - The Most Significant bit
NACK - Not Acknowledgement from receiver
OD - Open Drain
PEC - Packet Error Code
PP - Push Pull
Repeated Start - A repeated START is a START condition on the SMBus used to switch from
write mode to read mode in a combined format protocol (e.g. Byte Read). The repeated START
always follows an Acknowledge, and it always indicates that an address phase is beginning.
Slave-receiver - A Slave-receiver is a device that acts as a bus slave in a SMBus transaction
while it is receiving address, command or other data from a device acting as a bus master in the
transaction.
Slave-transmitter - A Slave-transmitter is a device acting as a bus slave in a SMBus
transaction while it is transmitting data on the bus in response to a bus master’s request.
4.2 SMBus overview
Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL). Each
device connected to the bus is software addressable by a unique address and a simple
master/slave relationships exist at all times. Masters can operate as master-transmitters or as
master-receivers. It’s a true multi-master bus including collision detection and arbitration to
prevent data corruption if two or more masters simultaneously initiate data transfer. Serial, 8-bit
oriented, bi-directional data transfers can be made at up to 100 kbit/s. The System Management
Bus (SMBus) is a two-wire interface through which various system component chips can
communicate with each other and with the rest of the system. It is based on the principles of
operation of I2C protocol. Multiple devices, both bus masters and bus slaves, may be connected
to a SMBus segment. Generally, a bus master device initiates a bus transfer between it and a
single bus slave and provides the clock signals. The one exception to this rule is during initial
bus setup when a single master may initiate transactions with multiple slaves simultaneously. A
bus slave device can receive data provided by the master or it can provide data to the master.
Only one device may master the bus at any time. Since more than one device may attempt to
take control of the bus as a master, the SMBus protocol provides an arbitration mechanism that
relies on the wired-AND connection of all SMBus device interfaces to the SMBus.