User Manual

Application Note
SMBus communication with MLX90614
390119061402 Page 10 of 32 Jan-2008
Rev 004
5 Comparing the I2C Bus to the SMBus
The I2C bus and the SMBus are popular 2-wire buses that are essentially compatible with each
other. Normally devices, both masters and slaves, are freely interchangeable between both
buses. Both buses feature addressable slaves (although specific address allocations can vary
between the two). The buses operate at the same speed, up to 100kHz, but the I2C bus has
both 400kHz and 2MHz versions. Complete compatibility between both buses is ensured only
below 100kHz. Here are explored the significant differences between I2C and SMB.
5.1 Timeout and Clock Speed differences
Timeout and (as a consequence of timeout) minimum clock speed are the most important
differences between the I2C bus and the SMBus.
I2C Bus = DC (no timeout)
SMBus = 10kHz (35mS timeout)
Timeout is where a slave device resets its interface whenever SCL goes low for longer than the
timeout, typically 35mSec. Use of a timeout also dictates a minimum speed for the clock,
because it can never go static. Thus, the SMBus has a minimum-clock-speed specification. By
comparison, the I2C bus can go static indefinitely. In the I2C bus, either a master or a slave can
hold the clock low as long as necessary to process data. In the I2C bus, if the slave locks up
and holds either SCL or SDA low, error recovery is impossible. Very few slave devices actually
have the ability to hold SCL. As a result, the most common bus error is slave devices that have
ended up in a state where SDA is low. In the I2C bus, a master accomplishes error recovery by
clocking SCL until SDA is high and then issuing a Start followed by a Stop.
In contrast to the I2C bus, SMBus slaves are expected to reset their interface whenever SCL is
low for longer than the timeout specified in the SMBus specification of 35mS.
SMBus specifies t
LOW: SEXT
as the cumulative clock low extend time for a slave device. I2C does
not have a similar specification. SMBus specifies t
LOW: MEXT
as the cumulative clock low extend
time for a master device. Again I2C does not have a similar specification.
5.2 DC specifications differences
Both I2C and SMBus are capable of operating with mixed devices that have either fixed input
levels (such as Smart Batteries) or input levels related to VDD. When mixing devices, the I2C
specification defines the VDD to be 5.0 Volt +/- 10% and the fixed input levels to be 1.5 and 3.0
Volts. Instead of relating the bus input levels to VDD, SMBus defines them to be fixed at 0.8 and
2.1 Volts. This SMBus specification allows for bus implementations with VDD ranging from 3 to
5 Volts +/- 10%.
I2C specifies the maximum leakage current to be 10 µA while SMBus version 1.0 specified
maximum leakage current of 1 uA. Version 1.1 of the SMBus specification relaxes the leakage
requirements to 5 µA, in order to reduce the cost of testing of SMBus devices.
While I
2
C defines maximum bus capacitance 400pF SMBus does not specify a maximum bus
capacitance. Instead it specifies the I
PULLUP
maximum of 350µA in Low-power DC specification
and minimum 4mA in High-power DC specification. Bus capacitance can be calculated taking
into consideration the maximum rise time and I
PULLUP
.
In the table below are given a summery of level specifications for the I2C Bus and the SMBus.
Table 4
High I
2
C VDD Dependent 0.7*V
DD
I
2
C Fixed 3.0V
SMBus 2.1V