User's Manual

MeiG hardware design guide
14
Figure 4.17: Backlight Drive Circuit
Note: 1. The backlight circuit should select the chip according to the backlight circuit of LCD. Users
should carefully read the LCD document and select the correct driver chip. The reference circuit
provided in this document is a series-type PWM dimming backlight driver circuit; if a series-type one-
line dimming backlight driver circuit (such as KTD2801) is used due to design requirements, GPIO is
required for control.
4.6.2 MIFI camera Interface
The SLM756P module supports the MIPI interface Camera and provides a dedicated camera power supply. The main
camera is a CSI0 interface that supports two sets of data lines and can support 8M pixels. The front camera is a CSI1
interface that supports a set of data lines and can support 5M pixels. The module provides the power required by
the Camera, including AVDD-2.85V, IOVDD-1.8V, DVDD-1.2V and AFVDD-2.8V (powering the focus motor).
Table 4.6: MIPI Camera Interface Definition
Main camera interface
Name
Pin
Input/Output
Description
MIPI_CSI0_LANE0_N
16
I/O
Rear Camera MIPI data signal
MIPI_CSI0_LANE0_P
17
I/O
MIPI_CSI0_LANE1_N
18
I/O
MIPI_CSI0_LANE1_P
19
I/O
MIPI_CSI0_CLK_N
20
I/O
Rear Camera MIPIclock signal
MIPI_CSI0_CLK_P
21
I/O
Rear Camera MIPIclock signal
CAM0_MCLK
14
I/O
Rear Camera main clock
CAM0_RST_N
12
I/O
Rear Camera reset signal
CAM0_PWDN
13
I/O
Rear Camera sleep signal
CAM_I2C_SDA
23
I/O
I2Csignal,CAMdedicated
CAM_I2C_SCL
24
I/O
I2Csignal,CAMdedicated
VREG_L6_1P8
7
O
1.8V IOVDD
VREG_L17_2P85
8
O
2.8V AVDD
VREG_L8_2P9
9
O
2.9V AFVDD（powering the focus motor）
VREG_L2_1P2
6
O
1.2V DVDD
Front camera interface
Name
Pin
Input/Output
Description
MIPI_CSI1_LANE0_N
26
I/O
Front Camera MIPIdata signal
MIPI_CSI1_LANE0_P
27
I/O
MIPI_CSI1_CLK_N
29
I/O
Front Camera MIPIclock signal
MIPI_CSI1_CLK_P
30
I/O
Front Camera MIPIclock signal
CAM1_MCLK
31
I/O
Front Camera main clock
CAM1_RST_N
32
I/O
Front Camera reset signal
CAM1_PWDN
33
I/O
Front Camera sleep signal