User's Manual

MeiG hardware design guide
12
4.6 MIPI Interface
The SLM756P supports the Moble Industry Processor Interface (MIPI) interface for Camera andLCM.
The module supports up to HD (720P) display, of which MIPI interface Main Camera supports up to
8MP and Front Camera supports 5MP.
MIPI is a high-speed signal line. In the Layout stage, please strictly follow the impedance and length
requirements to control the length of the differential pair within the group and the group length. The
total length should be as short as possible.
4.6.1 LCD Interface
The SLM756P module supports the LCD display of the MIPI interface with an identification signal for
the compatible screen. The resolution of the screen can be up to 1280*720. The signal interface is
shown in the following table. In the Layout, the MIPI signal line should strictly control the differential
100 ohm impedance and the equal length between the signal line group and the group.
The module's MIPI interface is a 1.2V power domain. When the user needs a compatible screen design,
the module's GPIO or ADC pin can be used. At the same time, the module can provide 2.8V power to
the LCD. The LCD interface is as follows:
Table 4.5: Interface Definitions
Name
Pin
Input/Output
Description
LCD_RST
117
O
LCM Reset Pin
MIPI_DSI0_CLK_N
119
O
MIPI Clock Line
MIPI_DSI0_CLK_P
120
O
MIPI_DSI0_LANE0_N
121
I/O
MIPI Data Line
MIPI_DSI0_LANE0_P
122
I/O
MIPI_DSI0_LANE1_N
123
I/O
MIPI_DSI0_LANE1_P
124
I/O
MIPI_DSI0_LANE2_N
125
I/O
Information/design
guidance
Comments
750 MHz
1.5 Gbit/s per lane
Main route 100 Ω ± 3%
Break-out 100 Ω ± 10%
Connector 100 Ω ± 20%
Main route 50 Ω ± 20%
Break-out 50 Ω ± 30%
Connector 50 Ω ± 30%
0.7 mm (5 ps)
It is important to maintain differential lines; single line
meandering should not be used other than at Tx breakout.
1.4 mm (10 ps)
This target is for compliance mode. For mission mode while
data rate is 1 Gbps or less, inter-pair skew may be relaxed
to 100 ps; consider 100 ps for extra-cable inter-pair time
skew. At 1.0-1.5 Gbps, this value is 50 ps. (Refer to the
MIPI Alliance Specfication for D-PHY 9.2.1 for mission-mode
target).
30 cm
This max length guidance is practical level of definition.
(Refer to the MIPI Alliance Specfication for D-PHY 7.6.1).
Spacing to
all other signal
4x line width
If not practical, may be relaxed to x3 line width by
accepting potential risk.
(Refer to the MIPI Alliance Specfication for D-PHY 7.6.5).
Spacing data
lane to lane
3x line width
If not practical, may be relaxed to x2 line width by
accepting potential risk.
(Refer to the MIPI Alliance Specfication for D-PHY 7.6.5).
Inspected by TDR simulation @ 150 ps (20‒80%).
No manufacturing variation considered.
Intra-lane length match
Data to clock slew
Max trace length
Length match
Spacing
Main route
Metrics
General
information
CLK frequency
Data rate
Differential
Single-ended
Impedance