User's Manual

MeiG hardware design guide
11
Figure 4.14: TX Connection Diagram
Figure 4.15: RX Connection Diagram
Note: When using Levels 14 and 15 for level isolation, you need to pay attention to the output
timing of VREG_L6_1P8. Only after VREG_L6_1P8 is output normally, the serial port can
communicate normally. VREG_L6_1P8 will enter low power mode when sleeping. If the serial
port needs to be in sleep mode. When communicating, please use the commonly used 1.8V as
the pull-up power supply.
Table 4.4: Serial Port Hardware Parameters
Description
Minimum
Maximum
Unit
Input low level
-
0.63
V
Input high level
1.17
-
V
Input low level
-
0.45
V
Input high level
1.35
-
V
Note: 1. The serial port of the module is a CMOS interface, and the RS232 signal cannot be
directly connected. If necessary, please use the RS232 conversion chip.
2. If the 1.8V output of the module cannot meet the high level range of the user
terminal, please add a level shifting circuit.