User's Manual

MeiG hardware design guide
21
123
MIPI_DSI0_LANE1_N
AI, AO
MIPI display serial interface 0 lane 1 negative
124
MIPI_DSI0_LANE1_P
AI, AO
MIPI display serial interface 0 lane 1 positive
125
MIPI_DSI0_LANE2_N
AI, AO
MIPI display serial interface 0 lane 2 negative
126
MIPI_DSI0_LANE2_P
AI, AO
MIPI display serial interface 0 lane 2 positive
127
GPIO36
GPIO36*
B-PD:nppukp
Configurable I/O
128
GPIO90_KEY_VOL_U
P
GPIO90*
DI;B-PD:nppukp
Configurable I/O Keypad sense bit 0
129
GPIO98
GPIO98*
B-PD:nppukp
Configurable I/O
130
GPIO95
GPIO95*
B-PD:nppukp
Configurable I/O
*Wake-up system interrupt pin
**Power chipPM8909pin
BBidirectionaldigital with CMOS input
HHigh-voltage tolerant
NPpdpukp=defaultno-pull with programmable options following the colon (:)
PDnppukp=defaultpulldownwith programmable options following the colon (:)
PUnppdkp=defaultpullupwith programmable options following the colon (:)
KPnppdpu=defaultkeeperwith programmable options following the colon (:)
Table 3.3Multiplexing function
GPIO
Module pin
BLSP Multiplexing functiondefault is blue
Outside BLSP
Other functions
SPI
UART
I2C
GPIO0
92
MOSI
I2S/GPIO
GPIO1
91
MISO
I2S/GPIO
GPIO2
90
CS_N
I2S/GPIO
GPIO3
89
CLK
I2S/GPIO
GPIO4
82
MOSI
TX
GPIO
GPIO5
81
MISO
RX
GPIO
GPIO6
59
CS_N
CTS
SDA
GPIO
GPIO7
58
CLK
RTS
SCL
GPIO
GPIO8
116
MOSI
GPIO
GPIO9
10
MISO
GPIO
GPIO10
11
CS_N
SDA
GPIO
GPIO11
83
CLK
SCL
GPIO
GPIO12
74
MOSI
GPIO
GPIO13
73
MISO
GPIO