User's Manual

MeiG hardware design guide
20
86
RF_MAIN
AI,AO
RF signal-Main ANT
87
GND
GND
GND
88
UIM1_DET_N
GPIO56
DI,B-PD:nppukp
Configurable I/O UIM1 removal detection
89
GPIO3
GPIO3
B-PD:nppukp
Configurable I/O, MI2S_2_D1
90
GPIO2
GPIO2
B-PD:nppukp
Configurable I/O,MI2S_2_D0
91
GPIO1
GPIO1
B-PD:nppukp
Configurable I/O,MI2S_2_SCK
92
GPIO0
GPIO0
B-PD:nppukp
Configurable I/O,MI2S_2_WS
93
GND
GND
GND
94
VREG_L11_SDC
PO
PMIC output 2.95V
95
SDC2_SDCARD_DET
GPIO38*
B-PD:nppukp
Configurable I/O ,SD_DET_N
96
SDC2_SDCARD_CMD
BH-PD:nppukp
Secure digital controller 2 command
97
SDC2_SDCARD_CLK
BH-NP:pdpukp
Secure digital controller 2 clock
98
SDC2_SDCARD_D0
BH-PD:nppukp
Secure digital controller 2 data bit 0
99
SDC2_SDCARD_D1
BH-PD:nppukp
Secure digital controller 2 data bit 1
100
SDC2_SDCARD_D2
BH-PD:nppukp
Secure digital controller 2 data bit 2
101
SDC2_SDCARD_D3
BH-PD:nppukp
Secure digital controller 2 data bit 3
102
GND
GND
GND
103
VREG_L15_UIM2
PO
PMIC supply for UIM2
104
UIM2_RESET
DO,B-PD:nppukp
Configurable I/O UIM2 reset
105
UIM2_DATA
B,B-PD:nppukp
Configurable I/O UIM2 data
106
UIM2_CLK
DO,B-PD:nppukp
Configurable I/O UIM2 clock
107
VREG_L14_UIM1
PO
PMIC supply for UIM1
108
UIM1_RESET
DO,B-PD:nppukp
Configurable I/O UIM1 reset
109
UIM1_DATA
B,B-PD:nppukp
Configurable I/O UIM1 data
110
UIM1_CLK
DO,B-PD:nppukp
Configurable I/O UIM1 clock
111
GND
GND
GND
112
USB_DM
AI, AO
USB data minus
113
USB_DP
AI, AO
USB data plus
114
USB _ID
AI
USB ID
115
GND
GND
GND
116
GPIO8_SPI_MOSI
GPIO8
B-PD:nppukp
Configurable I/O SPI
117
LCD_RST_N
GPIO25*
B-PD:nppukp
Configurable I/O,
#DSI_RST# ,MDP_VSYNC_S
118
GND
GND
GND
119
MIPI_DSI0_CLK_N
AO
MIPI display serial interface 0 clock – negative
120
MIPI_DSI0_CLK_P
AO
MIPI display serial interface 0 clock –positive
121
MIPI_DSI0_LANE0_N
AI, AO
MIPI display serial interface 0 lane 0 – negative
122
MIPI_DSI0_LANE0_P
AI, AO
MIPI display serial interface 0 lane 0 –positive