Specifications
specified
would
be
0000.
Since
all
logical addresses are greater than or equal
to
0000,
then
the
CPU's
entire
logical address
space
would
be
mapped
into the physical address
space
of
bank
A.
If
bits
6
and
7
were
set
and
bit
5
were
clear
(I-register
=
C0),
then logical addresses
between
gggg
and
BFFF
would
be
mapped
onto
physical
addresses in
bank
B,
whiLe
logicaL
addresses equal to or
above
C000
wouLd
be
mapped
onto physical addresses in
bank
A.
To
read or write the contents of the
I-register
the
ZSO's
LD
A,I
and
LD
I,A
instructions
are used. After
changing
the
vaLue
in
the
I-register,
the
new
boundary
wi
Ll
take
effect
after
the next
opcode
fetch.
Consider
the following
code
sequence:
LD
A,BDYVAL
LD
I,A
RET
iLOAD
A
WITH
NEW
BOUNDARY
VALUE
iLOAD
I
WITH
VALUE
iRETURN
The
return address
used
for the
RET
instruction
wiLL
be
popped
off the stack in the
memory
bank
determined
by
the
new
boundary
vaLue
in the
I-register,
whereas
the
opcode
for the
RET
instruction
wiLL
be
fetched
from
the
memory
bank
in effect prior to loading the
new
value into
the
I-register.
Note
that the
use
of the
ZSO
I-register
for seLecting bank-switching boundaries precludes
its
usuaL
use
in the
ZSO
Mode
2 (vectored)
interrupt.
It
might
appear that a
difficulty
with
this
method
of bank-switching
is
that there
is
no
logi cal address
which
maps
onto
any
physi cal address
above
E000
in
bank
B,
that
is,
that the
top
8k
of
bank
B cannot
be
directly
accessed
by
the
CPU.
This would
seem
to
be
the
case
because the highest
8k
address
boundary
which
can
be
specified
by
bits
5, 6,
and
7 of the
1-
register
is
E000,
so
that logical addresses
above
E000
wi
II always
be
mapped
onto physical
addresses
in
bank
A,
and
never
in
bank
a This
probLem
can
be
overcome
through the
use
of the
MPA
TYPE
and
PAGE
MODE
bits
of the
SAM,
as
expLained
beLow.
The
MAP
TYPE
bit
in the
SAM
(designated
'7Y'~
aLlows
addresses in
either
the
upper
of the
Lower
halves of the
64k
logical address
space
to
be
effectively translated into the other half
of the logicaL address space.
In
the "normal"
mode
of operation (the
mode
which
is
initial
ized
at
power-up)
the
TY
bit
is set.
In
this
mode,
each
logical address
is
mapped
onto a unique
physical address
in
bank
A
or
bank
B
by
mapping
process described previously.
If,
however,
the
TY
bit
is cleared, then the
upper
and
lower
haLves
of the
64k
logical address
space
map
onto a
physical address space
whose
size is
between
32k
and
64k.
The
actual size
and
location of the
physical
address space
within
the two
Main
Memory
Banks
is
determined
by
both
the
bank-
switching
boundary
set
'-"
in
the
I-register
and
by
the
PAGE
MODE
bit
in the
SAM
(designated
"P1"), as described
below.
With
both
the
MAP
TYPE
and
the
PAGE
MODE
bits
cleared, the position of the bank-switch
boundary
will
determine
both
the
bank
into
which
the
logicaL
addresses
are
mapped
as
well as
whether the
mapping
is
one-to-one or many-to-one.
Consider
first
the simplest case,
where
the
bank-switch
boundary
is
8000hex.
In
this
special case, logical addresses less than the bank-
switch
boundary
will
be
mapped
into the
physicaL
address
space
of
bank
B,
just
as
they
would
be
if
the
MAP
TYPE
b
it
were
set
("Norma
lit
mode).
However,
log
i
ca
l addresses
equa
l to or greater
than the bank-switch
boundary
are
mapped
alto
physical addresses in the 'bottom" half of
bank
A.
This part of the
physi
cal address space of
bank
A is the space into
whi
ch
logi cal address
from
0
to
7FFFhex
are
mapped
when
the bank-switch
boundary
is set to
0000
and
the
MAP
TYPE
bit
is
set
(normal
mode).
Thus
logical address
from
8000
to
FFFFhex
are essentialLy translated
to
0000
to
7FFFhex.
Note,
however
that
this
is
still
a one-to-one
mapping,
since
each
half of the
logical address space
is
mapped
into the
bottom
half of a
distinct
Main
Memory
Bank.
Continuing with the
case
where
the bank-switch
boundary
is
at
8000hex
and
the
MAP
TYPE
bit
cleared, the
effect
of the
PAGE
MODE
bit
is to determine
whether
it
is
the
upper
or
lower
half
of the logical address
space
which
is
mapped
into a ''foreign'' part of the physical address
space.
As
explained
above,
if
the
PAGE
MODE
bit
is
cleared, the
upper
half of the logical
address space
is
mapped
into the
bottom
half of
bank
A,
whiLe
the
lower
half
is
mapped
into the
lower
half
of
bank
B.
If,
instead,
the
PAGE
MODE
bit
is
set,
then
the
upper
half
of
the
logical space
wi
II be
mapped
into the
LPper
half
of
bank
A.
This
is
the physical space into
which
the
upper
half of the logical space
would
be
mapped
if
the
MAP
TYPE
bit
were
set.
The
Megatel
Computer
Technologies Toronto,
Canada
Page
H/W-5