Specifications
Megatel
QUARK
CPU
Overview
------------------------------------
-----,--------------------
The
Megatel
QUARK
uses the
I80B
microprocessor, manufactured
by
lilog
Inc.
The
180B
clock
frequency
is
5.97MHz
(6.2MHz
on
50
Hz
models), leading to
an
execution time of
667ns
(645ns
on
50
Hz
models)
for a typical 4-cycle instruction,
such
as
a
register-to-register
ADD.
The
main
memory
of
the
QUARK
is
either
64/128/256kbytes in size. A
memory-management
scheme
employing the
18OB's
I-register
is
used
to provide simple yet
flexible
bank-switching
to
allow the
full
use
of the extended physical
memory.
The
Synchronous
Address
Multiplexer
(SAM)
also
participates
in the
memory-mapping
process,
and
permits the use of
some
special
mapping
modes.
To
accomodate the
Video
Display Interface, the
main
memory
of the
QUARK
operates as a
dual-ported
RAM.
One
of the ports
is
a bidirectional input/output port
to
the
CPU,
while the
other port
is
essentially
an
unidirectional output-only port for the
Video
Display Interface.
Through
the programmable registers of the
SAM,
the size
and
location of the area of
main
memory
used
as
the
Video
Display
Memory
can
be
set
under
software control.
As
a consequence of the operation of
this
dual-ported
memory,
all
180B
memory
cycles
have
wait
states
added
to extend
them
to a multiple of 4 T-states.
Thus
an
instruction
which
would
execute in, say, 7 T-states
if
no
wait
states
were
added
wi
II
have
one
wait
state
added,
to
extend the instruction to 8 cycles.
The
insertion of these wait
states
is
fundamental
to
the
synchronization of
memory
accesses
by
the
Video
Display Interface
and
by
the
cpu.
Input/output
instructions
are
also
extended
to
modulo-4
cycles,
but then have four
additional wait
states
added.
For
instance,
an
11-state
IN
A,r
type of instruction
will
have
a
total
of five wait
states
added, extending
it
to
16T-states.
The
addition of the extra four
cycles relaxes the
speed
requirements for the peripheral controller devices, both those
on
the
board
as
well
as
user-added external controllers.
CPU
Memory
Management
The
I80B
processor
used
on
the
QUARK
has
a sixteen-bit address bus,
and
is
therefore able
to
di
rect ly address
65536
(64k)
locat ions
in
memory.
However,
the
QUARK
has
128k
of
memory,
and
therefore a process
is
required
whereby
the
64k
possible addresses generated
by
the
CPU
are
"mapped"
into the
128k
of
main
memory
provided.
In
this
discussion, the addresses generated
by
the
CPU
on
its
Address
Bus
wi
II
be
called "logical addresses", whereas the actual locations in
memory
where
data
is
stored
will
be
called
'~hysical
addresses'~
Logical
addresses
are
therefore the hexidecimal values normally
used
in
programming.
The
ISO's
I-register
and
the
Synchronous
Address
Multiplexer
(SAM)
are
used
in the
mapping
process between the logical
and
physical address spaces.
The
I-register
is
used
to
control
bank-switching
between
bank
A
and
bank
B of the
main
memory,
and
to determine in
which
bank
the
Video
Display
Memory
is located.
The
SAM
determines the location of the
Video
Display
Memory
within a
64k
address space,
and
controls the
mapping
of the upper
and
lower halves of the
logical address space.
The
most-significant three
bits
(bits
5, 6,
and
7)
of the
I-register
are used
to
define
an
8k
address
boundary
within the
CPU's
64k
logical address space.
Any
logical address appearing
on
the
Address
Bus
is
compared
to the address
boundary
as determined
by
these
bits.
The
result
of
this
comparison
determines in
which
memory
bank
the physical address is
to
be
found.
If
the value of the logical address
is
greater than or equal to the specified address
boundary,
the
logical
address
wi
II
be
mapped
onto a
physical
address
(that
is,
a
memory
location) in
memory
bank
A.
Conversely,
if
the value of the logical address
is
less than
this
boundary, then the logical address
wi
II
be
mapped
onto a physical address in
memory
bank
B.
For
example,
if
bits
5, 6,
and
7 of the
I-register
were
all
zero, then the address
boundary
Megatel
Computer
Technologies Toronto,
Canada
Page
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