Specifications
TABLE
lIb
TIMER-1
BAUD
RATES
FOR
FULL-DUPLEX
INTERFACE
-
60HZ
VERSION
BAUD
DIVIDE
BY
1
DIVIDE
BY
16
DIVIDE
BY
64
RATE
VALUE
(HEX)
ERROR
VALUE
(HEX)
ERROR
VALUE
(HEX)
ERROR
---_
..
_-
--
--
19200
37
0025
.23%
1
0001-11.73%
9600
76
004C
-.10
3
0003
2.20
7200
102
0066
-.18
5
OOOS
-4.10
4800
154
009A
-.26
8
0008
-.42
1
0001
-11.73
3600
20S
OOCD
.19 B
OOOB
1.54
2
0002
-13.69
2400
309
0135
-.02
18
0012
-1.68
3
0003
2.20
1800
413
019D
-.12
24
0018
.55 5
OOOS
-4.10
1200
620
026C
-.06
37
0025
.23
8
0008
-.42
600
1241
O4D9
.03
76
004C
-.10
17
0011
.23
300
2484
09B4
-.01
154
009A
-.26
37
0025
.23
150
4969
1369
.01
309
0135
-.02
76
004C
-.10
134.5
5542
15A6
.01
345
0159
-.07
85
0055
-.14
110
6m
1A79
.00
422
01A6
-.02
104
0068
.16
75
9941
26D5
.00
620
026C
-.06
154
009A
-.26
50
14912
3A40
.00
930
03A2
.04
231
OOE7
.12
-----
*
Not
reconmended.
Use
the Divide-by-16
mode.
---
-
_.
-- .
-----
Notes
for Table
II(a)
and
II(b)
1.
The
frequency of the
Timer
1-generated clock output
on
PB7
of the
VIA
is
given
by
fE/(2N+3.5),
where
fE
is
the frequency of the E-clock
and
N
is
the value in the
Timer
1
latch.
The
baud
rate is
this
frequency divided
by
1,
16, or 64, according
to
the divide
ratio
bits
in
the
ACIA.
2.
Baud
rates other than those
shown
above
are possible
by
loading the
Timer
1 latches whith
the value determined
by
the equation above. Consult the data sheets for the
VIA
(6522A)
and
the
ACIA
(68A50).
3.
Baud
rate
errors
exceeding
out
5%
may
be
unacceptabLe in
some
applications.
If
this
is
the case, Timer-2
may
be
used
to
generate the Transmit
and
Receive
cLocks
for the FuLl-
dupLex
port.
To
do
this,
instaLL
jumpers
J3
and
J4,
set
PB7
of the
VIA
to
act as
an
input,
and
use the Timer-2 generated
baud
rates (Table
IlIa)
for the
ACIA
Transmit
and
Receive cLocks.
4.
In
the divide-by-one
mode,
the
ACIA
receiver clock
shouLd
be
synchronized with the
incoming
data.
The
ACIA
transmitter
wiLL
operate normally in
this
mode.
Megatel
Computer
Technologies Toronto,
Canada
Appendix
Page
A-5