Specifications
Summary
of Shift Register output
modes
(ACR-4
= 1)
ACR-3
ACR-2
Remarks
o
o
o
1
1
o
1
1
Continuous shifting
at
T2
rate.
Useful for waveform-generation applications.
8
bits
only shifted
at
T2
rate
after
each
SR
load.
SR
Interrupt
Flag
set
after
8
bits
shifted.
8
bits
only shifted
at
E-clock rate
after
each
SR
load.
SR
Interrupt
Flag
set
after
8
bits
shifted.
8
bits
or
more
shifted
at
CB1
input
rate.
SR
Interrupt
Flag
set
after
8
bits
shifted.
Install
J3
&
J4
for
Timer
1 clock
to
CB1
input.
With
ACR
bit
2
and
3 cleared,
Timer
2 determines the rate at
which
data
is
shifted out of
the
S~
In
this
mode,
shifting is continuous,
and
does
not
stop automatically
after
eight
bits
have been
shifted.
This
mode
can
be
used
for
generating
retangular
waveforms
(repeating
patterns of eight
bits)
on
pin
A-4.
This
might
be
useful in
some
applications for generating
audio signals.
In the next
mode
(ACR-2=1,
ACR-3=O),
shifting stops automatically
after
eight
bits
are
shifted,
and
the
SR
Interrupt
Flag
in the Interrupt
Flag
Register
(IFR)
of the
VIA
is
set.
If
the
SR
Interrupt
Enable
bit
in
the Interrupt
Enable
Register (bit 2 of the
IER)
is
set,
the
VIA
will
assert
its
Interrupt
Request
output,
which
will
cause a
Z80
interrupt
if
the
Z80's
interrupt system
is
enabled.
The
shifting rate
is
determined
by
Ti
mer
2, as in the previous
mode.
This is the
mode
used
by
the Serial Printer
Handler
included in the Operating
System.
The
next
mode
(ACR-2=O,
ACR-3=1)
operates
in
the
same
manner
as
the previous
mode,
except
that the
System
E-clock
is
used
as
the
shift
clock, rather than
Timer
2.
The
frequency of the
E-clock
is
1.49MHz
for
60Hz
models,
and
1.55MHz
for
50Hz
modeLs.
In
the
final
mode
(ACR-2=1,
ACR-3=1),
the
shift
rate
is
controLled
by
pulses appl ied
to
1
the
CB1
input
on
the
VIA.
If
jumpers
J3
and
J4
are instalLed, then the
PB7
I/O
line
wi
II
be
connected to the
CB1
line
(as
well
as
to the Transmit
and
Receive
clocks
on
the
ACIA
- see
Sec
3.3).
This
allows
Ti
mer
1, normally
used
to generate the
baud
rates for the
ACIA,
to also
generate the
shift
clock for the Shift Register.
Note
that
J5
must
not
be
installed in
this
mode,
or the
CB1
clock input will
be
shorted to the
CB2
SR
output.
For
serial
input, the Shift Register,
and
the
CB1
and
CB2
control lines are
used.
In
this
mode,
data is shifted into the
SR
on
the
CB2
line.
Pin
B-2
on
the
QUARK's
connector provides
an
RS-232C
compatible input
line
for
the
Simplex Port input
mode.
Jumper J7 should
be
installed
to allow the signal
from
pin
B-2
to
reach
the
CB2
input
on
the
VIA.
(Note
that J8,
installed at the factory unless ordered otherwise, will connect
CB2
and
PB6
together
when
J7
is
installed.
If
both
J7
and
J8
are
installed,
PB6
must
be configured
as
an
input or
it
will
contend
with the signal
at
CB2.)
In
order for the Shift Register to be
used
in the input
mode,
bit
4 of the
ACR
must
be
cleared.
As
in the output
mode,
bits
2
and
3 of the
ACR
wi
II determine the rate at
which
the
SR
is
shifted,
as
well
as
its
operational
mode.
Megatel
Computer
Technologies Toronto,
Canada
Page
H/W-18