Specifications
------------------------------------------------------------------------------
Bit-mapped
Graphics
Mode
In
the
Bit-mapped
Graphics Mode,
the
Monochrome Video
Display
Interface
fetches
data
from
the
Video
Display
Memory
in
exactly
the
same manner
as
is
used
in
the
Alphanumeric
mode.
However,
instead
of
this
data
going
to
the
character
generator
(together
with
the
three
Scan
Line
Counter
bits),
the
data
goes
directly
to
the
Video
Shift
Register.
Thus
the
patterns
of
"ones" and
"zeroes"
stored
in
each
byte
of
the
displayed
portion
of
the
Video
Display
Memory
will
directly
determine
which
oots,
or
pixels,
are
illuminated
on
the
CRT.
Because
the
Character
Generator
is
not used
to
map
eight-bit
bytes
onto
eight-by-eight
dot
patterns
in
the
Graphics
Mode,
eight
times
as
much
memory
must
be
allocated
for
the
Video
Display
Memory
when
operating
in
Graphics
Mode
as
when
in
Alphanumeric
mode.
Note, however
that
in
Graphics
mode
the
96-byte
blocks
scanned
for
each
raster
line
displayed
are
contiguous
in
the
QUARK's
Main Memory, whereas
in
Alphanumeric Mode,
these
blocks
have
32-byte
gaps
between each
block.
Thus
the
actual
memory
area
used
in
Graphics
mode
need
be
only
six
times
that
used
for
Alphanumeric mode.
The
size
of
the
Video
Display
Memory
is
increased
by moving
its
starting
address
oownward
within
the
Main
Memory.
To
switch
between
the
Bit-mapped
Graphics
Mode
and Alphanumeric Mode,
the
Graphics
Mode
Bit
of
the
QUARK
and
the
V2
Mode
bit
of
the
SAM
must
be
changed. The
Graphics
Mode
Bit
is
bit
6
of
the
PIA
Port
B
output
(1/0
address
76hex). The Graphi
cs
Mode
bit
is
at
a
logic
low
level
for
Graphics
Mode
and a
logic
high
level
for
Alphanumeric
Mode.
This
bit
is
cLeared by
writing
to
Port
B
with
accumulator
bit
6
set
to
zero,
and
is
set
by
writing
to
the
same
port
with
the
same
accumulator
bit
set
to
one.
Note
that
bit
6
of
the
PIA
Data
Direction
Register
(1/0
address
74hex> must be high
in
order
that
PB6
be enabLed
as
an
output
Line. The
V2
Mode
bit
of
the
SAM
must
be
set
to
1
for
the
Graphi
cs
Mode, and
cleared
for
the
Alphanumeri c
Mode.
The
V0
and
V1
mode
bits
are
left
cleared
in
both
display
modes.
The
Graphics
Mode
bit
and
the
V2
mode
bit
must be changed
in
synchrony
with
the
Vertical
Sync (vS)
signal.
A
suggested
approach
using
the
Real-time
Clock
interrupt
(which
is
generated
by
the
positive-going
edge
of
the
VS
signaL>
to
initiate
the
sequence
of
mode
bit
changes
is
described
below.
When
the
Real-time
CLock
interrupt
occurs,
create
a deLay
of
at
least
five
microseconds.
This
delay
ensures
that
the
seven
pulses
(at
the
E-clock
frequency)
immediately
following
the
first
rising
edge
of
the
VS
signal
will
be
bypassed.
At
the
end
of
this
delay,
load
the
new
starting
address
of
the
Video
Display
Memory
(defined
by
bits
F0-F3, FS, and
F6)
into
the
SAM.
Then change
the
polarity
of
the
active
transition
on
the
CA1
input
of
the
PIA
from
positive-
transition
active
to
negative-transition
active.
<This
requires
that
bit
1
of
the
PIA
Control
Register
A be
set
low.)
Now
wait
for
the
negative
transition
of
the
VS
signal
by
poLling
the
PIA
IRQA1
flag
(bit
7
of
Control
Register
A,
1/0
address
75hex). ImmediateLy upon
detecting
this
negative
transition
change
the
Graphics
mode
bit
and
the
V2
bit
of
the
SAM
to
the
values
requi
red
for
the
mode
to
be
selected.
After
changing
these
bits
restore
the
original
value
of
bit
1
of
the
PIA
Control
Register
A
by
Loading
a one
into
this
bit.
This
completes
the
sequence
of
operations
required
to
change from Alphanumeric
mode
to
Graphics
mode.
The
following
routine
can
be
calLed
to
enter
into
the
Graphic
Mode.
It
is
assumed
here
that
the
Real-time
Clock
interrupt
is
disabled
before
entering
the
routine.
iGraphics-entry
exampLe
routine
irevised
sept
15,
1983
to
restore
piacra
and
eliminate
unnecessary
isync
loops
.
,
SAMV2S
EQU
SAMF0C
EQU
SAMF1C
EQU
SAMF2C
EQU
SAMF3S
EQU
SAMFSC
EQU
SAMF6C
EQU
0FF85H
iADDRESS
TO
SET
V2
BIT
IN
SAM
0FF86H
iADDRESS
TO
CLEAR
F0
BIT
IN
SAM
0FF88H
iADDRESS
TO
CLEAR
F1
BIT
IN
SAM
0FF8AH
iADDRESS
TO
CLEAR
F2
BIT
IN
SAM
0FF8DH
iADDRESS
TO
SET
F3
BIT
IN
SAM
0FF90H
iADDRESS
TO
CLEAR
F5
BIT
IN
SAM
0FF92H
iADDRESS
TO
CLEAR
F6
BIT
IN
SAM
Megatel Computer
Technologies
Toronto,
Canada
Page
H/W-12