User`s guide

Universal Library User's Guide Analog Input Boards - PCI-DAS4020 Series
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Trigger" input on the 40-pin connector (P3). Use the A/D Start Trigger input for the cbAInScan() and
cbFileAInScan() functions, and AInScan() and FileAInScan() methods. For the cbAPretrig() or
cbFilePretrig() functions, and the APretrig() or FilePretrig() method, use the A/D Stop Trigger
input.
When using both EXTCLOCK and EXTTRIGGER options, one of the signals (either clock or trigger) must be
assigned to the Trig/Ext Clk BNC input. The function of the Trigger BNC is determined by the setting of
"Trig/Ext Clock Mode" in InstaCal. The Trig/Ext Clock BNC can be set to function as either the trigger ("A/D
Start Trigger") or the clock ("A/D External Clock"). Pin 10 on the 40-pin connector then assumes the opposite
function.
Analog hardware triggering supported. The trigger source can be set via InstaCal to any of the analog BNC
inputs. cbSetTrigger()/SetTrigger() is supported for TRIGBELOW and TRIGABOVE trigger types. Analog
thresholds are set relative to the voltage range set in the scan. For example, using a range of BIP1VOLTS during
a cbAInScan()/AInScan(), (0) corresponds to –1 volt (V) and 4095 corresponds to +1 V.
When using the cbAPretrig() function or the APretrig() method, use either the TRIGGER BNC or pin 8 of
the 40 pin connector. To use the BNC, set InstaCal "Trig/Ext Clock Mode" to A/D Stop Trigger; otherwise, if
not set to this selection, pin 8 of the 40-pin connector is used.
When using cbAPretrig()/APretrig() with EXTCLOCK, the two inputs are required. The TRIGGER BNC
can be set to function as either the pacer clock or the trigger. For the BNC to be setup as the pacer clock, set
InstaCal "Trig/Ext Clk Mode" to A/D External Clock. To use the BNC as the trigger, set this InstaCal option
to A/D Stop Trigger. If neither of these selections are used, the 40-pin connector will be used for both inputs;
pin 8 will be input for A/D Stop Trigger, and pin 10 will be input for the pacer clock signal.
Digital (TTL) hardware gating supported. The gate source can be set via InstaCal to either the "Trig/Ext Clk"
BNC input or the "A/D Pacer Gate" input on the 40-pin connector (P3).
Analog hardware gating supported. Analog thresholds are set relative to the voltage range set in the scan. For
example, using a range of BIP1VOLTS during a cbAInScan()/AInScan(), (0) corresponds to (-1V) and 4095
corresponds to +1V.
The gate must be in the active (enabled) state before starting an acquisition.
For EXTCLOCK or EXTTRIGGER (digital triggering) using the BNC connector, InstaCal provides a configuration
setting for thresholds. The selections available are either 0 V or 2.5 V. Use 0 V if the incoming signal is
BIPOLAR. Use the 2.5 V option if the signal is UNIPOLAR, for example, standard TTL.
When using both EXTCLOCK and EXTTRIGGER options, one of the signals (either clock or trigger) must be
assigned to the Trig/Ext Clk BNC input.
Memory configuration
In order to achieve the maximum sample rate under some conditions, a contiguous area of memory must be
set up. The following is a guide that can be used to determine whether or not you need to set up this memory,
and how to accomplish it using InstaCal.
If the number of samples you are acquiring is less than 2k samples (2,048), then you do NOT need to set up
contiguous memory (leave the Memory Size edit box in InstaCal at zero).
If you are acquiring more than 2,048 samples, contiguous memory may be required, depending on sample
rate. Use the table below to determine if contiguous memory is required.