User`s guide

Universal Library User's Guide Analog Input Boards - PCI-DAS4020 Series

DataValue 0 to 255 for FIRSTPORTA or FIRSTPORTB;

0 to 15 for FIRSTPORTCL or FIRSTPORTCH

BitNum 0 to 23 for FIRSTPORTA

Counter I/O

Counter functions and methods supported

None

Triggering

Trigger functions and methods supported

UL: cbSetTrigger()

UL for .NET: SetTrigger()

Trigger argument values

TrigType TRIGPOSEDGE, TRIGNEGEDGE, TRIGABOVE, TRIGBELOW, GATEHIGH, GATELOW,

GATENEGHYS, GATEPOSHYS, GATEABOVE, GATEBELOW, GATEINWINDOW, GATEOUTWINDOW

Threshold 0 to 4095

Event notification

Event notification functions and methods supported

UL: cbEnableEvent(), cbDisableEvent()

UL for .NET: EnableEvent(), DisableEvent()

Event notification argument values

EventType ON_SCAN_ERROR, ON_PRETRIGGER†, ON_DATA_AVAILABLE, ON_END_OF_AI_SCAN

Hardware considerations

Pacing analog input

Hardware pacing, external or internal clock supported. The clock source can be set via InstaCal to either the

"Trig/Ext Clk" BNC input or the "A/D External Clock" input on the 40 pin connector (P3). Configuring for

the BNC clock input will disable the clock input (pin 10) on the 40-pin connector. When the EXTCLOCK option

is used, the clock signal presented to the "Trig/Ext Clk" BNC input or the "A/D External Clock" input is

divided by 2 in one or two channel mode and is divided by 4 in four channel mode. If both EXTCLOCK and

EXTTRIGGER are used, both the Trigger BNC and pin 10 on the 40-pin connector require signals. This is

further explained in the "Triggering and gating" section below. When using EXTCLOCK, the Rate argument is

used by the Universal Library to calculate the appropriate chain size. Set the Rate argument to the

approximate rate used by the external clock to pace acquisitions.

When executing cbAInScan()/AInScan() with the EXCLOCK option, the first three clock pulses are used to set

up the PCI-DAS4020/12, and the first sample is actually taken on the fourth clock pulse.

The packet size varies. See "Memory configuration" on page 46 for more information.

Triggering and gating

Digital (TTL) hardware triggering supported. The trigger source can be set via InstaCal to either the

"Trig/Ext Clk" BNC input, the "A/D Start Trigger" input on the 40-pin connector (P3) or the "A/D Stop

† The EventData for ON_PRETRIGGER events may not be accurate. In general, this value is below the actual number of

pretrigger samples available in the buffer.