User`s manual

Counter Section
Counter type 82C54
Configuration Two 82C54 devices. three down-counters per 82C54, 16 bits each
82C54A: (Counters #1, 2, & 3)
Counter 0 - ADC residual sample counter.
Source: ADC Clock.
Gate: Programmable source.
Output: End-of-Acquisition interrupt.
Counter 1 - ADC Pacer Lower Divider
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Output: Chained to Counter 2 Clock.
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Output: ADC Pacer clock (if software selected), available at user
connector.
82C54B: (Counters #4, 5 &6)
Counter 0 - Pretrigger Mode
Source: ADC Clock.
Gate: External trigger
Output: End-of-Acquisition interrupt.
Counter 0 - Non-Pretrigger Mode: User counter 4
Source: User input at 100-pin connector or internal 10 MHz
(software selectable)
Gate: User input at 100-pin connector.
Output: Available at 100-pin connector.
Counter 1 - DAC Pacer Lower Divider
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Output: Chained to Counter 2 Clock.
Counter 2 - DAC Pacer Upper Divider
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Output: DAC Pacer clock, available at user connector.
Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min High, 50 ns min Low
Gate width high 50 ns min (high or low)
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min
Environmental
Operating temperature range 0 to 70°C
Storage temperature range
−
40 to 100°C
Humidity 0 to 90% non-condensing
Power Consumption
Icc: Operating (A/D converting to FIFO) 2.0A typical, 2.1A max
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