User`s manual

7 SPECIFICATIONS
Typical for 25 DegC unless otherwise specified.
Analog Input Section
A/D converter type AD976ABN
Resolution 16 bits
Programmable ranges ±10V, ±5V, ±2.5V, ±1.25V, 0 to 10V, 0 to 5V, 0 to 2.5V, 0 to 1.25V
A/D pacing Programmable: internal counter or external source
Data transfer From 512 sample FIFO via REPINSW, int, software-polled
Bust mode Programmable option at 5 µs sample intervals during burst
Polarity Unipolar/Bipolar, software-selectable
Number of channels 8 differential or 16 single-ended, software-selectable
Interrupts INTA# - mapped to IRQn via PCI BIOS at boot-time
Interrupt enable Programmable
A/D conversion time 5 µs
Throughput 200 kHz min
Differential Linearity error (Bipolar) ±1 LSB
Integral Linearity error (Bipolar)
1
±1.5 LSB
Differential Linearity error (Unipolar) ±1 LSB
Integral Linearity error (Unipolar)
2
±1.5 LSB
Gain Error ±10V, 0 to 10V Ranges: 22.5 ppm Max
±5V, 0 to 5V Ranges: 22.5 ppm Max
±2.5V, 0 to 2.5V Ranges: 22.5 ppm Max
±1.25,V 0 to 1.25V Ranges: 22.5 ppm typical, 45 ppm Max
No missing codes guaranteed 16 bits
Gain drift (A/D specs) ±20 ppm/°C, all ranges
Zero drift (A/D specs) ±10 ppm/°C, all ranges
Input leakage current (@25 Deg C) 200 nA
Input impedance Min 10 MegOhms
Absolute maximum input voltage ±15V
A/D Triggering Modes Digital:
Software-configurable for Edge (triggered) or level-activated (gated).
Programmable polarity (rising/falling edge trigger, high/low gate).
Analog:
Software-configurable for above/below reference, in/out window and
hysteresis.
Programmable polarity (rising/falling edge trigger, high/low gate).
Trigger levels set by DAC0 and/or DAC1.
Pre-trigger:
Unlimited pre- and post-trigger samples. Total # of samples must be >256.
Compatible with both Digital and Analog trigger options.
27
2
Integral linearity for 1.25V unipolar is specified at ±3LSB max
1
Integral linearity for 1.25V bipolar is specified at ±3LSB max