User`s manual

Table of Contents
1
INTRODUCTION
........................................................ 1
2
INSTALLATION
........................................................ 1
2.1 SOFTWARE INSTALLATION ............................................ 1
2.2 HARDWARE INSTALLATION ........................................... 2
2.3 CONNECTING SIGNALS TO THE PCI-DAS1602/16 .......................... 3
2.4 ANALOG INPUT CONNECTIONS ........................................ 3
2.4.1 Single-Ended ........................................................ 3
2.4.2 Floating Differential ................................................... 3
2.4.3 Differential .......................................................... 4
3
FUNCTIONAL OVERVIEW
............................................... 5
4
SELF-CALIBRATION
................................................... 6
4.1 ANALOG INPUT CALIBRATION ......................................... 6
4.2 ANALOG OUTPUT CALIBRATION ....................................... 7
5
PROGRAMMING & APPLICATIONS
...................................... 8
5.1 PROGRAMMING LANGUAGES .......................................... 8
5.2 PACKAGED APPLICATIONS PROGRAMS ................................. 8
6
REGISTER ARCHITECTURE
............................................. 9
6.1 BADR0 ............................................................... 9
6.2 BARD1 ............................................................... 9
6.2.1 Interrupt / ADC FIFO Register .......................................... 9
6.2.2 ADC Channel MUX and Control Register ................................. 12
6.2.3 Trigger Control/Status Register ......................................... 13
6.2.4 Calibration Register .................................................. 16
6.2.5 DAC Control/Status Register ........................................... 18
6.3 BADR2 .............................................................. 19
6.3.1 ADC Data Register .................................................. 19
6.3.2 ADC FIFO Clear Register ............................................. 20
6.4 BADR3 .............................................................. 20
6.4.1 ADC Pacer Clock Data and Control Registers .............................. 21
6.4.2 High Drive Digital I/O Data and Control Registers .......................... 22
6.4.3 DAC Pacer Clock Data and Control Registers .............................. 23
6.5 BADR4 .............................................................. 25
6.5.1 DAC Data Register .................................................. 25
6.5.2 DAC FIFO Clear Register ............................................. 26
7
SPECIFICATIONS
...................................................... 27