User`s manual

6.5 BADR4
The BADR4 contains the shared DAC data register and the DAC FIFO clear register.
6.5.1 DAC Data Register
BADR4 + 0
DAC Data register. A Write-only register.
WRITE
DA0DA1DA2DA3DA4DA5DA6DA7DA8DA9DA10DA11DA12DA13DA14DA15
0123456789101112131415
MSB LSB
DA[15:0]
These bits represent the DAC data word. Format is dependent upon offset mode as
described below:
Bipolar Mode: Offset Binary Coding
0000 h =
−
FS
7FFFh = Mid-scale
(0V)
FFFFh = +FS
−
1LSB
Unipolar Mode: Straight Binary Coding
0000 h =
−
FS (0V)
7FFFh = Mid-scale (+FS/2)
FFFFh = +FS
−
1LSB
Paced DAC operations require that the FIFO be loaded with the appropriate data. A REP OUTSW
instruction to this address will do this. It is important to note that the FIFO is the shared data source
between DAC0 and DAC1. Care must be taken to ensure that DAC0 data always precedes DAC1 data
during simultaneous operations. Target DAC selection is made via the
HS[1:0]
bits described earlier in
section 6.2.5, DAC Control/Status Register, BADR1 + 8.
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