User`s manual

8254B COUNTER 1 DATA
- DAC PACER DIVIDER LOWER
BADR3 + 9
READ/WRITE
D0D1D2D3D4D5D6D7
01324567
8254B COUNTER 2 DATA
- DAC PACER DIVIDER UPPER
BADR3 + Ah
READ/WRITE
D0D1D2D3D4D5D6D7
01324567
Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is fed to the clock input
of Counter 2 which provides the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is
a precision 10 MHz oscillator source.
Counter 2's output is called the 'Internal Pacer' and can be selected by software to the be the ADC Pacer
source. Counters 1 and 2 should be configured to operate in 8254 Mode 2.
8254B CONTROL REGISTER
BADR3 + Bh
WRITE ONLY
D0D1D2D3D4D5D6D7
01324567
The control register is used to set the operating Modes of 8254 Counters 0,1 & 2. A counter is configured
by writing the correct Mode information to the Control Register, then the proper count data must be
written to the specific Counter Register.
The Counters on the 8254 are 16-bit devices. Since the interface to the 8254 is only 8-bits wide, Count
data is written to the Counter Register as two successive bytes. First the low byte is written, then the high
byte. The Control Register is 8-bits wide. Further information can be obtained on the 82C54 data sheet,
available from Intel or Harris.
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