User`s manual

The following table contains codes for the possible I/O Port configurations for the HDIO:

Table 6-14. I/O Port Configuration Coding

271BININININ1111

261AOUTINININ0111

2519INOUTININ1011

2418OUTOUTININ0011

1913ININOUTIN1101

1812OUTINOUTIN0101

1711INOUTOUTIN1001

1610OUTOUTOUTIN0001

11BINININOUT1110

10AOUTININOUT0110

99INOUTINOUT1010

88OUTOUTINOUT 0010

33ININOUTOUT1100

22OUTINOUTOUT0100

11INOUTOUTOUT1000

00OUTOUTOUTOUT0000

DECIMALHEXPORT C

LOWER

PORT BPORT C

UPPER

PORT AD0D1D3D4

6.4.3 DAC Pacer Clock Data and Control Registers

8254B COUNTER 0 DATA

- ADC PRE-TRIGGER INDEX COUNTER

BADR3 + 8

READ/WRITE

D0D1D2D3D4D5D6D7

01324567

Counter 0 of the DAC 8254 device is actually used as the ADC Pre-Trigger index counter. This counter

serves to mark the boundary between pre- and post-trigger samples when the ADC is operating in

Pre-Trigger Mode. The External ADC Trigger flip-flop gates Counter 0 ON; the ADC FIFO Half-Full

signal gates it OFF.

Knowing the desired number of post-trigger samples, software can then calculate how many 1/2 FIFO

data packets need to be collected and what corresponding residual sample count needs to be written to

BADR3 + 0.