User`s manual

6.4.1 ADC Pacer Clock Data And Control Registers
8254A COUNTER 0 DATA -
ADC RESIDUAL SAMPLE COUNTER
BADR3 + 0
READ/WRITE
D0D1D2D3D4D5D6D7
01324567
Counter 0 is used to stop the acquisition when the desired number of samples have been gathered. It is
gated on when a 'residual' number of conversions remain. Counter 0 will be enabled by use of the
ARM
bit (BADR1 + 4).
Counter 0 is to operated in Mode 0.
8254A COUNTER 1 DATA
- ADC PACER DIVIDER LOWER
BADR3 + 1
READ/WRITE
D0D1D2D3D4D5D6D7
01324567
8254A COUNTER 2 DATA
- ADC PACER DIVIDER UPPER
BASE + 2
READ/WRITE
D0D1D2D3D4D5D6D7
01324567
Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is fed to the clock input
of Counter 2 which provides the upper 16 bits of the pacer clock divider. The clock input to Counter 1 is
a precision 10 MHz oscillator source.
Counter 2 output is called the 'Internal Pacer' and can be selected by software to be the ADC Pacer
source. Configure Counters 1 & 2 to operate in 82C54 Mode 2.
ADC 82C54 CONTROL REGISTER
BADR3 + 3
WRITE ONLY
D0D1D2D3D4D5D6D7
01324567
The control register is used to set the operating modes of 82C54 Counters 0, 1, and 2. A counter is
configured by writing the correct mode information to the control register followed by a count written to
the specific counter register.
The counters on the 82C54 are 16-bit devices. Since the interface to the 82C54 is only eight bits wide,
count data is written to the Counter Register as two successive bytes. First the low byte is written, then
the high byte. The Control Register is eight bits wide. Further information can be obtained on the 82C54
data sheet, available from Intel or Harris.
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