User`s manual

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15

0123456789101112131415

MSB LSB

AD[15:0]

This register contains the current ADC data word. Data format is dependent upon offset

mode:

Bipolar Mode: Offset Binary Coding

0000 h =

−

7FFFh = Mid-scale

(0V)

FFFFh = +FS

−

1 LSB

Unipolar Mode: Straight Binary Coding

0000 h =

−

FS (0V)

7FFFh = Mid-scale (+FS/2)

FFFFh = +FS

−

1 LSB

6.3.2 ADC FIFO Clear Register

BADR2 + 2 ADC FIFO Clear register. This is a Write-only register. A write to this address location

clears the ADC FIFO. Data is don't care. The ADC FIFO should be cleared before all new ADC

operations.

6.4 BADR3

The I/O Region defined by BADR3 contains data and control registers for the ADC Pacer, DAC Pacer,

Pre/Post-Trigger Counters and High-Drive Digital I/O bytes. The PCI-DAS1602/16 has two 8254

counter/timer devices. These are referred to as 8254A and 8254B and are assigned as

shown in Table 6-13 below:

Table 6-13. Counter/Timer Modes

DAC Pacer Upper Divider28254B

DAC Pacer Lower Divider18254B

ADC Pre-Trigger Index/User Counter08254B

ADC Pacer Upper Divider28254A

ADC Pacer Lower Divider18254A

ADC Post-Trigger Sample Counter08254A

FunctionCounter #Device

NOTE: All reads/writes to BADR3 are

byte

operations.